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[/] [i2c/] [trunk/] [rtl/] [vhdl/] [i2c_master_top.vhd] - Blame information for rev 51

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---------------------------------------------------------------------
2
----                                                             ----
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----  WISHBONE revB2 compl. I2C Master Core; top level           ----
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----                                                             ----
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----                                                             ----
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----  Author: Richard Herveille                                  ----
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----          richard@asics.ws                                   ----
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----          www.asics.ws                                       ----
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----                                                             ----
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----  Downloaded from: http://www.opencores.org/projects/i2c/    ----
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----                                                             ----
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---------------------------------------------------------------------
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----                                                             ----
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---- Copyright (C) 2000 Richard Herveille                        ----
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----                    richard@asics.ws                         ----
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----                                                             ----
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---- This source file may be used and distributed without        ----
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---- restriction provided that this copyright statement is not   ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer.----
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----                                                             ----
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----     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ----
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---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ----
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---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ----
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---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ----
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---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ----
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---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ----
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---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ----
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---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ----
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---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ----
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---- LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ----
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---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ----
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---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ----
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---- POSSIBILITY OF SUCH DAMAGE.                                 ----
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----                                                             ----
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---------------------------------------------------------------------
37
 
38
--  CVS Log
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--
40 51 rherveille
--  $Id: i2c_master_top.vhd,v 1.7 2004-03-14 10:17:03 rherveille Exp $
41 15 rherveille
--
42 51 rherveille
--  $Date: 2004-03-14 10:17:03 $
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--  $Revision: 1.7 $
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--  $Author: rherveille $
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--  $Locker:  $
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--  $State: Exp $
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--
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-- Change History:
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--               $Log: not supported by cvs2svn $
50 51 rherveille
--               Revision 1.6  2003/08/09 07:01:13  rherveille
51
--               Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
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--               Fixed a potential bug in the byte controller's host-acknowledge generation.
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--
54 38 rherveille
--               Revision 1.5  2003/02/01 02:03:06  rherveille
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--               Fixed a few 'arbitration lost' bugs. VHDL version only.
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--
57 34 rherveille
--               Revision 1.4  2002/12/26 16:05:47  rherveille
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--               Core is now a Multimaster I2C controller.
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--
60 31 rherveille
--               Revision 1.3  2002/11/30 22:24:37  rherveille
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--               Cleaned up code
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--
63 27 rherveille
--               Revision 1.2  2001/11/10 10:52:44  rherveille
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--               Changed PRER reset value from 0x0000 to 0xffff, conform specs.
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--
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67
 
68
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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72
entity i2c_master_top is
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        generic(
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                ARST_LVL : std_logic := '0'                   -- asynchronous reset level
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        );
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        port (
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                -- wishbone signals
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                wb_clk_i  : in  std_logic;                    -- master clock input
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                wb_rst_i  : in  std_logic := '0';             -- synchronous active high reset
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                arst_i    : in  std_logic := not ARST_LVL;    -- asynchronous reset
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                wb_adr_i  : in  unsigned(2 downto 0);         -- lower address bits
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                wb_dat_i  : in  std_logic_vector(7 downto 0); -- Databus input
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                wb_dat_o  : out std_logic_vector(7 downto 0); -- Databus output
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                wb_we_i   : in  std_logic;                    -- Write enable input
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                wb_stb_i  : in  std_logic;                    -- Strobe signals / core select signal
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                wb_cyc_i  : in  std_logic;                    -- Valid bus cycle input
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                wb_ack_o  : out std_logic;                    -- Bus cycle acknowledge output
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                wb_inta_o : out std_logic;                    -- interrupt request output signal
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90
                -- i2c lines
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                scl_pad_i     : in  std_logic;                -- i2c clock line input
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                scl_pad_o     : out std_logic;                -- i2c clock line output
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                scl_padoen_o  : out std_logic;                -- i2c clock line output enable, active low
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                sda_pad_i     : in  std_logic;                -- i2c data line input
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                sda_pad_o     : out std_logic;                -- i2c data line output
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                sda_padoen_o  : out std_logic                 -- i2c data line output enable, active low
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        );
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end entity i2c_master_top;
99
 
100
architecture structural of i2c_master_top is
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        component i2c_master_byte_ctrl is
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        port (
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                clk    : in std_logic;
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                rst    : in std_logic; -- synchronous active high reset (WISHBONE compatible)
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                nReset : in std_logic;  -- asynchornous active low reset (FPGA compatible)
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                ena    : in std_logic; -- core enable signal
107 15 rherveille
 
108 27 rherveille
                clk_cnt : in unsigned(15 downto 0);      -- 4x SCL
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                -- input signals
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                start,
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                stop,
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                read,
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                write,
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                ack_in : std_logic;
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                din    : in std_logic_vector(7 downto 0);
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118 27 rherveille
                -- output signals
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                cmd_ack  : out std_logic;
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                ack_out  : out std_logic;
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                i2c_busy : out std_logic;
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                i2c_al   : out std_logic;
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                dout     : out std_logic_vector(7 downto 0);
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125 27 rherveille
                -- i2c lines
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                scl_i   : in std_logic;  -- i2c clock line input
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                scl_o   : out std_logic; -- i2c clock line output
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                scl_oen : out std_logic; -- i2c clock line output enable, active low
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                sda_i   : in std_logic;  -- i2c data line input
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                sda_o   : out std_logic; -- i2c data line output
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                sda_oen : out std_logic  -- i2c data line output enable, active low
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        );
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        end component i2c_master_byte_ctrl;
134
 
135
        -- registers
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        signal prer : unsigned(15 downto 0);             -- clock prescale register
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        signal ctr  : std_logic_vector(7 downto 0);      -- control register
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        signal txr  : std_logic_vector(7 downto 0);      -- transmit register
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        signal rxr  : std_logic_vector(7 downto 0);      -- receive register
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        signal cr   : std_logic_vector(7 downto 0);      -- command register
141
        signal sr   : std_logic_vector(7 downto 0);      -- status register
142 15 rherveille
 
143
        -- internal reset signal
144
        signal rst_i : std_logic;
145
 
146 31 rherveille
        -- wishbone write access
147
        signal wb_wacc : std_logic;
148
 
149 27 rherveille
        -- internal acknowledge signal
150
        signal iack_o : std_logic;
151
 
152 15 rherveille
        -- done signal: command completed, clear command register
153
        signal done : std_logic;
154
 
155
        -- command register signals
156
        signal sta, sto, rd, wr, ack, iack : std_logic;
157
 
158 31 rherveille
        signal core_en : std_logic;                      -- core enable signal
159
        signal ien     : std_logic;                      -- interrupt enable signal
160 15 rherveille
 
161
        -- status register signals
162 27 rherveille
        signal irxack, rxack : std_logic;                -- received aknowledge from slave
163 31 rherveille
        signal tip           : std_logic;                -- transfer in progress
164
        signal irq_flag      : std_logic;                -- interrupt pending flag
165
        signal i2c_busy      : std_logic;                -- i2c bus busy (start signal detected)
166
        signal i2c_al, al    : std_logic;                -- arbitration lost
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168
begin
169
        -- generate internal reset signal
170
        rst_i <= arst_i xor ARST_LVL;
171
 
172
        -- generate acknowledge output signal
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        gen_ack_o : process(wb_clk_i)
174 15 rherveille
        begin
175 27 rherveille
            if (wb_clk_i'event and wb_clk_i = '1') then
176
              iack_o <= wb_cyc_i and wb_stb_i and not iack_o;         -- because timing is always honored
177
            end if;
178
        end process gen_ack_o;
179
        wb_ack_o <= iack_o;
180 31 rherveille
 
181
 
182
        -- generate wishbone write access signal
183
        wb_wacc <= wb_cyc_i and wb_stb_i and wb_we_i;
184 15 rherveille
 
185 27 rherveille
        -- assign wb_dat_o
186
        assign_dato : process(wb_clk_i)
187
        begin
188
            if (wb_clk_i'event and wb_clk_i = '1') then
189
              case wb_adr_i is
190
                when "000"  => wb_dat_o <= std_logic_vector(prer( 7 downto 0));
191
                when "001"  => wb_dat_o <= std_logic_vector(prer(15 downto 8));
192
                when "010"  => wb_dat_o <= ctr;
193
                when "011"  => wb_dat_o <= rxr; -- write is transmit register TxR
194
                when "100"  => wb_dat_o <= sr;  -- write is command register CR
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196 27 rherveille
                -- Debugging registers:
197
                -- These registers are not documented.
198
                -- Functionality could change in future releases
199
                when "101"  => wb_dat_o <= txr;
200
                when "110"  => wb_dat_o <= cr;
201
                when "111"  => wb_dat_o <= (others => '0');
202
                when others => wb_dat_o <= (others => 'X');     -- for simulation only
203
              end case;
204
            end if;
205 15 rherveille
        end process assign_dato;
206
 
207
 
208 31 rherveille
        -- generate registers (CR, SR see below)
209
        gen_regs: process(rst_i, wb_clk_i)
210 15 rherveille
        begin
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            if (rst_i = '0') then
212
              prer <= (others => '1');
213
              ctr  <= (others => '0');
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              txr  <= (others => '0');
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            elsif (wb_clk_i'event and wb_clk_i = '1') then
216
              if (wb_rst_i = '1') then
217
                prer <= (others => '1');
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                ctr  <= (others => '0');
219
                txr  <= (others => '0');
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              elsif (wb_wacc = '1') then
221
                case wb_adr_i is
222
                   when "000" => prer( 7 downto 0) <= unsigned(wb_dat_i);
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                   when "001" => prer(15 downto 8) <= unsigned(wb_dat_i);
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                   when "010" => ctr               <= wb_dat_i;
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                   when "011" => txr               <= wb_dat_i;
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                   when "100" => null; --write to CR, avoid executing the others clause
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228 31 rherveille
                   -- illegal cases, for simulation only
229
                   when others =>
230
                      report ("Illegal write address, setting all registers to unknown.");
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                      prer <= (others => 'X');
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                      ctr  <= (others => 'X');
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                      txr  <= (others => 'X');
234
                end case;
235
              end if;
236
            end if;
237
        end process gen_regs;
238 15 rherveille
 
239
 
240 31 rherveille
        -- generate command register
241
        gen_cr: process(rst_i, wb_clk_i)
242
        begin
243
            if (rst_i = '0') then
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                cr <= (others => '0');
245 31 rherveille
            elsif (wb_clk_i'event and wb_clk_i = '1') then
246 38 rherveille
                if (wb_rst_i = '1') then
247
                    cr <= (others => '0');
248
                elsif (wb_wacc = '1') then
249
                    if ( (core_en = '1') and (wb_adr_i = 4) ) then
250
                        -- only take new commands when i2c core enabled
251
                        -- pending commands are finished
252
                        cr <= wb_dat_i;
253
                    end if;
254
                else
255
                    if (done = '1' or i2c_al = '1') then
256
                        cr(7 downto 4) <= (others => '0'); -- clear command bits when command done or arbitration lost
257
                    end if;
258 31 rherveille
 
259 38 rherveille
                    cr(2 downto 1) <= (others => '0');   -- reserved bits, always '0'
260
                    cr(0) <= '0';                        -- clear IRQ_ACK bit
261
                end if;
262 27 rherveille
            end if;
263 31 rherveille
        end process gen_cr;
264 27 rherveille
 
265 15 rherveille
        -- decode command register
266
        sta  <= cr(7);
267
        sto  <= cr(6);
268
        rd   <= cr(5);
269
        wr   <= cr(4);
270
        ack  <= cr(3);
271
        iack <= cr(0);
272
 
273
        -- decode control register
274
        core_en <= ctr(7);
275
        ien     <= ctr(6);
276
 
277
        -- hookup byte controller block
278 31 rherveille
        byte_ctrl: i2c_master_byte_ctrl port map (
279 15 rherveille
                clk      => wb_clk_i,
280
                rst      => wb_rst_i,
281
                nReset   => rst_i,
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                ena      => core_en,
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                clk_cnt  => prer,
284
                start    => sta,
285
                stop     => sto,
286
                read     => rd,
287
                write    => wr,
288
                ack_in   => ack,
289
                i2c_busy => i2c_busy,
290 31 rherveille
                i2c_al   => i2c_al,
291 15 rherveille
                din      => txr,
292
                cmd_ack  => done,
293
                ack_out  => irxack,
294
                dout     => rxr,
295
                scl_i    => scl_pad_i,
296
                scl_o    => scl_pad_o,
297
                scl_oen  => scl_padoen_o,
298
                sda_i    => sda_pad_i,
299
                sda_o    => sda_pad_o,
300
                sda_oen  => sda_padoen_o
301
        );
302
 
303
 
304
        -- status register block + interrupt request signal
305
        st_irq_block : block
306
        begin
307 27 rherveille
            -- generate status register bits
308
            gen_sr_bits: process (wb_clk_i, rst_i)
309
            begin
310
                if (rst_i = '0') then
311 31 rherveille
                  al       <= '0';
312 27 rherveille
                  rxack    <= '0';
313
                  tip      <= '0';
314
                  irq_flag <= '0';
315
                elsif (wb_clk_i'event and wb_clk_i = '1') then
316
                  if (wb_rst_i = '1') then
317 31 rherveille
                    al       <= '0';
318 27 rherveille
                    rxack    <= '0';
319
                    tip      <= '0';
320
                    irq_flag <= '0';
321
                  else
322 31 rherveille
                    al       <= i2c_al or (al and not sta);
323 27 rherveille
                    rxack    <= irxack;
324
                    tip      <= (rd or wr);
325 15 rherveille
 
326 27 rherveille
                    -- interrupt request flag is always generated
327 31 rherveille
                    irq_flag <= (done or i2c_al or irq_flag) and not iack;
328 27 rherveille
                  end if;
329
                end if;
330
            end process gen_sr_bits;
331 15 rherveille
 
332 27 rherveille
            -- generate interrupt request signals
333
            gen_irq: process (wb_clk_i, rst_i)
334
            begin
335
                if (rst_i = '0') then
336
                  wb_inta_o <= '0';
337
                elsif (wb_clk_i'event and wb_clk_i = '1') then
338
                  if (wb_rst_i = '1') then
339
                    wb_inta_o <= '0';
340
                  else
341
                    -- interrupt signal is only generated when IEN (interrupt enable bit) is set
342
                    wb_inta_o <= irq_flag and ien;
343
                  end if;
344
                end if;
345
            end process gen_irq;
346 15 rherveille
 
347 27 rherveille
            -- assign status register bits
348
            sr(7)          <= rxack;
349
            sr(6)          <= i2c_busy;
350 34 rherveille
            sr(5)          <= al;
351
            sr(4 downto 2) <= (others => '0'); -- reserved
352 27 rherveille
            sr(1)          <= tip;
353
            sr(0)          <= irq_flag;
354 15 rherveille
        end block;
355
 
356
end architecture structural;

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