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rherveille |
ncverilog: v03.40.(b001): (c) Copyright 1995 - 2001 Cadence Design Systems, Inc.
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ncverilog: v03.40.(b001): Started on Jun 15, 2002 at 13:36:36
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ncverilog
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+access+rwc
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+linedebug
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+define+"WAVES"
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+incdir+../../../../bench/verilog
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+incdir+../../../../rtl/verilog
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+libext+.v
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-y
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/tools/synopsys/dw/sim_ver/
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../../../../rtl/verilog/i2c_master_bit_ctrl.v
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../../../../rtl/verilog/i2c_master_byte_ctrl.v
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../../../../rtl/verilog/i2c_master_top.v
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../../../../bench/verilog/i2c_slave_model.v
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../../../../bench/verilog/wb_master_model.v
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../../../../bench/verilog/tst_bench_top.v
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ncverilog: *W,BADPRF: The +linedebug option may have an adverse performance impact.
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file: ../../../../rtl/verilog/i2c_master_bit_ctrl.v
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module worklib.i2c_master_bit_ctrl:v (up-to-date)
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errors: 0, warnings: 0
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file: ../../../../rtl/verilog/i2c_master_byte_ctrl.v
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module worklib.i2c_master_byte_ctrl:v (up-to-date)
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errors: 0, warnings: 0
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file: ../../../../rtl/verilog/i2c_master_top.v
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module worklib.i2c_master_top:v (up-to-date)
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errors: 0, warnings: 0
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file: ../../../../bench/verilog/i2c_slave_model.v
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module worklib.i2c_slave_model:v (up-to-date)
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errors: 0, warnings: 0
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file: ../../../../bench/verilog/wb_master_model.v
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module worklib.wb_master_model:v (up-to-date)
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errors: 0, warnings: 0
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file: ../../../../bench/verilog/tst_bench_top.v
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module worklib.tst_bench_top:v
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errors: 0, warnings: 0
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ncvlog: *W,LIBNOU: Library "/tools/synopsys/dw/sim_ver/" given but not used.
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Total errors/warnings found outside modules and primitives:
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errors: 0, warnings: 1
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Caching library 'worklib' ....... Done
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Elaborating the design hierarchy:
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Building instance overlay tables: .................... Done
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Generating native compiled code:
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worklib.tst_bench_top:v <0x7fb52c98>
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streams: 12, words: 59009
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Loading native compiled code: .................... Done
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Building instance specific data structures.
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Design hierarchy summary:
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Instances Unique
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Modules: 6 6
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Primitives: 2 1
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Registers: 68 68
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Scalar wires: 48 -
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Expanded wires: 36 2
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Vectored wires: 6 -
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Always blocks: 23 23
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Initial blocks: 3 3
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Cont. assignments: 28 28
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Pseudo assignments: 11 14
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Simulation timescale: 10ps
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Writing initial simulation snapshot: worklib.tst_bench_top:v
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Loading snapshot worklib.tst_bench_top:v .................... Done
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ncsim> source /cds/tools/inca/files/ncsimrc
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ncsim> run
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INFO: Signal dump enabled ...
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status: 0 Testbench started
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INFO: WISHBONE MASTER MODEL INSTANTIATED (tst_bench_top.u0)
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status: 19500 done reset
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status: 23600 programmed registers
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status: 25600 verified registers
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status: 27600 enabled core
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status: 30600 generate 'start', write cmd a0 (slave address+write)
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status: 2582600 tip==0
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status: 2585600 write slave memory address 01
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status: 4877600 tip==0
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status: 4880600 write data a5
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status: 7172600 tip==0
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status: 7175600 write next data 5a, generate 'stop'
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status: 9467600 tip==0
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status: 19467600 wait 100us
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status: 19470600 generate 'start', write cmd a0 (slave address+write)
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status: 22014600 tip==0
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status: 22017600 write slave address 01
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status: 24309600 tip==0
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status: 24312600 generate 'repeated start', write cmd a1 (slave address+read)
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status: 26858600 tip==0
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status: 26860600 read + ack
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status: 29154600 tip==0
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status: 29158600 read + ack
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status: 31448600 tip==0
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status: 31452600 read + ack
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status: 33744600 tip==0
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status: 33746600 received xx from 3rd read address
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status: 33748600 read + nack
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status: 36038600 tip==0
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status: 36040600 received xx from 4th read address
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status: 36043600 generate 'start', write cmd a0 (slave address+write). Check invalid address
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status: 38589600 tip==0
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status: 38592600 write slave memory address 10
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status: 40884600 tip==0
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status: 40884600 Check for nack
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status: 40886600 generate 'stop'
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status: 40888600 tip==0
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status: 43388600 Testbench done
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Simulation stopped via $stop(1) at time 433886 NS + 0
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/mnt/pooh/projects/I2C/bench/verilog/tst_bench_top.v:427 $stop;
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ncsim> exit
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ncverilog: v03.40.(b001): Exiting on Jun 15, 2002 at 13:47:48 (total: 00:11:12)
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