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[/] [i2c/] [trunk/] [sim/] [i2c_verilog/] [run/] [run] - Blame information for rev 68

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Line No. Rev Author Line
1 22 rherveille
#!/bin/csh
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3 61 rherveille
set i2c      = ../../..
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set bench    = $i2c/bench
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set wave_dir = $i2c/sim/rtl_sim/i2c_verilog/waves
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ncverilog                                                       \
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                                                                \
9 61 rherveille
        +access+rwc                                             \
10 22 rherveille
        +define+WAVES                                           \
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                                                                \
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        +incdir+$bench/verilog                                  \
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        +incdir+$i2c/rtl/verilog                                \
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                                                                \
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        $i2c/rtl/verilog/i2c_master_bit_ctrl.v                  \
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        $i2c/rtl/verilog/i2c_master_byte_ctrl.v                 \
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        $i2c/rtl/verilog/i2c_master_top.v                       \
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                                                                \
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        $bench/verilog/i2c_slave_model.v                        \
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        $bench/verilog/wb_master_model.v                        \
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        $bench/verilog/tst_bench_top.v
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