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rherveille |
/*
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Include file for OpenCores I2C Master core ////
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//// ////
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//// File : oc_i2c_master.h ////
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//// Function: c-include file ////
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//// ////
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//// Authors: Richard Herveille (richard@asics.ws) ////
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//// Filip Miletic ////
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//// ////
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//// www.opencores.org ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2001 Richard Herveille ////
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//// Filip Miletic ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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*/
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/*
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* Definitions for the Opencores i2c master core
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*/
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/* --- Definitions for i2c master's registers --- */
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/* ----- Read-write access */
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#define OC_I2C_PRER_LO 0x00 /* Low byte clock prescaler register */
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#define OC_I2C_PRER_HI 0x01 /* High byte clock prescaler register */
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#define OC_I2C_CTR 0x02 /* Control register */
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/* ----- Write-only registers */
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#define OC_I2C_TXR 0x03 /* Transmit byte register */
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#define OC_I2C_CR 0x04 /* Command register */
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/* ----- Read-only registers */
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#define OC_I2C_RXR 0x03 /* Receive byte register */
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#define OC_I2C_SR 0x04 /* Status register */
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/* ----- Bits definition */
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/* ----- Control register */
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#define OC_I2C_EN (1<<7) /* Core enable bit: */
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/* 1 - core is enabled */
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/* 0 - core is disabled */
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#define OC_I2C_IEN (1<<6) /* Interrupt enable bit */
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/* 1 - Interrupt enabled */
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/* 0 - Interrupt disabled */
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/* Other bits in CR are reserved */
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/* ----- Command register bits */
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#define OC_I2C_STA (1<<7) /* Generate (repeated) start condition*/
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#define OC_I2C_STO (1<<6) /* Generate stop condition */
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#define OC_I2C_RD (1<<5) /* Read from slave */
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#define OC_I2C_WR (1<<4) /* Write to slave */
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#define OC_I2C_ACK (1<<3) /* Acknowledge from slave */
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/* 1 - ACK */
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/* 0 - NACK */
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#define OC_I2C_IACK (1<<0) /* Interrupt acknowledge */
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/* ----- Status register bits */
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#define OC_I2C_RXACK (1<<7) /* ACK received from slave */
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/* 1 - ACK */
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/* 0 - NACK */
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#define OC_I2C_BUSY (1<<6) /* Busy bit */
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#define OC_I2C_TIP (1<<1) /* Transfer in progress */
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#define OC_I2C_IF (1<<0) /* Interrupt flag */
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/* bit testing and setting macros */
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#define OC_ISSET(reg,bitmask) ((reg)&(bitmask))
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#define OC_ISCLEAR(reg,bitmask) (!(OC_ISSET(reg,bitmask)))
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#define OC_BITSET(reg,bitmask) ((reg)|(bitmask))
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#define OC_BITCLEAR(reg,bitmask) ((reg)|(~(bitmask)))
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#define OC_BITTOGGLE(reg,bitmask) ((reg)^(bitmask))
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#define OC_REGMOVE(reg,value) ((reg)=(value))
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