Subversion Repositories i2c

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<b><font size=+2 face="Helvetica, Arial"

color=#bf0000>Project Name: I2C controller core</font></b>

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<font size=+1><b>Description</b></font>

<P>

I2C is a two-wire, bidirectional serials bus that provide a simple, efficient method of data exchange between devices.

<BR>

You can find I2C specification on <A HREF=http://www-us.semiconductors.philips.com/acrobat/various/I2C_BUS_SPECIFICATION_3.pdf> Phillips web Site</A>.

<br>

Work was originally started by Frédéric Renet. You can find his webpage <A href=http://www.opencores.org/cores/i2c/index_orig.shtml>here</A>.

<BR>

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<font size=+1><b>What you get</b></font><p>

<UL>

<li>WISHBONE rev.B2 compliant core

<li>No Multimaster operation

<li>No FIFO

<li>No slave mode

<li>Simple command based interface

</UL>

<p><font size=+1><b>Documentation</b></font><p>

<ul>

<li>Revision 0.4 of the WISHBONE I2C Master Core is available <A href=http://www.opencores.org/cgi-bin/cvsget.cgi/i2c/doc/i2c_rev04.pdf>here</A>.

</ul>

<p><font size=+1><b>Current status</b></font><p>

<ul>

<li>Design is available in VHDL and Verilog from OpenCores CVS via <a href="http://www.opencores.org/cvsweb.shtml/">cvsweb</a> or via <a href="/cvsmodule.shtml">cvsget</a></li>

<li>Note that the Verilog version is currently up-to-date. The VHDL version needs some modifications.</li>

</ul>

<p>

<font size=+1><b>Maintainer(s):</b></font><p>

<p><ul><a href=mailto:rherveille@opencores.org>Richard Herveille</A></ul>

<p><font size=+1><b>Mailing-list:</b></font><p>

<ul><a href=mailto:cores@opencores.org_NOSPAM>cores@opencores.org_NOSPAM</A></ul>

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