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[/] [i2c_master_slave_core/] [tags/] [t1/] [i2c_master_slave_core/] [verilog/] [rtl/] [shift.v] - Blame information for rev 6

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Line No. Rev Author Line
1 2 toomuch
////////////////////////////Shift.v/////////////////////////////////////////////////////////////////////
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//                                                                                                    //        
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//Design Engineer:      Ravi Gupta                                                                    //
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//Company Name   :      Toomuch Semiconductor
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//Email          :      ravi1.gupta@toomuchsemi.com                                                   //        
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//                                                                                                    //
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//Purpose        :      Used for shifting address and data in both transmit and recieve mode          //        
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//created        :      22-11-07                                                                      //
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//                                                                                                    //                                
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////////////////////////////////////////////////////////////////////////////////////////////////////////
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/*// synopsys translate_off
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`include "oc8051_timescale.v"
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// synopsys translate_on
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`include "oc8051_defines.v"*/
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module shift(clk,asyn_rst,load,shift_en,serial_in,data_in,serial_out,data_out);
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input   clk,asyn_rst,load,shift_en,serial_in;
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input   [7:0]data_in;
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output  serial_out;
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output  [7:0]data_out;
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reg     [7:0]data;
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always@(posedge clk or posedge asyn_rst or posedge load)
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begin
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        if(asyn_rst)
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                data<=8'h0;                             //clear the data register upon asynchronous reset.
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        else if(load)
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                data<=data_in;                          //Load the internal register upon insertion of load bit.
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        else if(shift_en)
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                data<={data[6:0],serial_in};             //Upon shift_en high every time a new serial data is coming to LSB bit and data will be shifted
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                                                        //to one bit.
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        else
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                data<=data;                             //Prevent formation of latches
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end
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assign data_out = data;                                 //Output the data in a data_register
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assign serial_out = data[7];                            //MSB is transmitted first in I2C protocol.
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endmodule
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//change loading into asynchronous mode         
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