OpenCores
URL https://opencores.org/ocsvn/i2c_master_slave_core/i2c_master_slave_core/trunk

Subversion Repositories i2c_master_slave_core

[/] [i2c_master_slave_core/] [trunk/] [i2c_master_slave_core/] [i2c_master_slave_core/] [svtb/] [Readme] - Blame information for rev 4

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 4 toomuch
 
2
This Directory contains all files which are required to run this VMM testbench.
3
Scripts are not given as it vary from compiler to compiler.
4
 
5
The Basic structure of file system is given below.
6
 
7
vmm_i2c_top.sv
8
|
9
|--- vmm_clkgen.sv
10
|--- vmm_program_test.sv
11
                |
12
                |--- vmm_i2c_env.sv (This is the environment file and all transactors and packet files
13
                                                        are included in this file)
14
 
15
Please note that for transition coverage in register testcase (write-write-read), another file is
16
availabe which is vmm_program1_test.sv. In this file Scenario_generator_class is extended and
17
program and top level module is also available.
18
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.