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[/] [i2c_master_slave_core/] [trunk/] [i2c_master_slave_core/] [verilog/] [rtl/] [controller_interface.v] - Blame information for rev 2

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////////////////////////////////////////////controller_interface.v////////////////////////////////////////
//                                                                                                      //
//Design Engineer:      Ravi Gupta                                                                      //
//Company Name   :      Toomuch Semiconductor
//Email          :      ravi1.gupta@toomuchsemi.com                                                     //
//                                                                                                      //      
//Purpose        :      This core will be used as an interface between I2C core and Processor           //                      
//Created        :      6-12-2007                                                                       //
//                                                                                                      //      
//                                                                                                      //
//                                                                                                      //
//                                                                                                      //      
//                                                                                                      //                      
//                                                                                                      //                      
//                                                                                                      //
//                                                                                                      //
//Modification : Change the control register,added halt reset and inter_rst in control register
/////////////////////////////////////////////////////////////////////////////////////////////////////////
 
/*// synopsys translate_off
`include "oc8051_timescale.v"
// synopsys translate_on
 
`include "oc8051_defines.v"*/
 
 
module processor_interface (clk,rst,add_bus,data_in,data_out,as,ds,rw,bus_busy,byte_trans,slave_addressed,arb_lost,slave_rw,inter,ack_rec,
                  core_en,inter_en,mode,master_rw,ack,rep_start,data,i2c_data,slave_add,time_out_reg,prescale,irq,time_out,inter_rst,halt,data_en,time_rst);
input clk;                      //System clock
input rst;                      //system reset
 
//signals connecting core to processor
/////////////////////////////////////
 
input [7:0]add_bus;              //contains address of internal register
input [7:0]data_in;              //trnasport the data for i2c core
input as;                       //asserted high indicates vallid address has been placed on the address bus
input ds;                       //asserted high indicates valid data on data bus
input rw;                       //"1" indicates that processor has to write else read
output irq;                     //interrupt to processor
output inter_rst;               //this bit will be written by processor when it will clear the interrupt.
output [7:0]data_out;
output halt;
output data_en;
input time_rst;
 
//signals from core to reflect te status of core and buses
///////////////////////////////////////////////////////////
 
input bus_busy;                 //signal from core indicates bus is busy
input byte_trans;               //signal from core indicates byte transfer is in progress
input slave_addressed;          //signal from core indicares core has been identified as slave
input arb_lost;                 //signal from core indicates bus error
input slave_rw;                 //signal from core indicates operation of slave core
input inter;                    //signal from core.this will interrupt the processor if this bit as well as interrupt enable is high
input ack_rec;                  //signal from core to reflect the status of ack bit
input time_out;
 
//bits of control register
//////////////////////////
 
inout core_en;                  //this bit must be cleared before any other bit of control register have any effect on core
inout inter_en;                 //To intrrupt the core this bit must be set when interrupt is pending
inout mode;                     //Transaction from "0" to "1" directes core to act as master else slave
inout master_rw;                //set directiion for master either to transmit or receive
inout ack;                      //value of acknowledgment bit to be transmitted on SDA line during ack cycle
inout rep_start;                //set this bit if processor wants a repeated start
 
//data register
////////////////
 
inout [7:0]prescale;             //contains the value for generating SCL frequency
inout [7:0]time_out_reg;         //contains the value for maximum low period for scl
inout [7:0]slave_add;            //this is the programmble slave address
inout [7:0]data;            //data for i2c core 
input [7:0]i2c_data;             //data from core for processor
 
//defining registers addresses
/////////////////////////////
 
`define         PRER    8'b0000_0010
`define         CTR     8'b0000_0100
`define         SR              8'b0000_1000
`define         TO              8'b0000_1010
`define         ADDR    8'b0000_1100
`define         DR              8'b0000_1110
`define         RR              8'b0000_0000
 
/*//defing the machine state
//////////////////////////
 
parameter       processor_idle=2'b00;
parameter       processor_address=2'b01;
parameter       processor_data=2'b10;
parameter       processor_ack=2'b11;*/
 
//Definig internal registers and wires
/////////////////////////////////////
 
wire core_en,inter_en,mode,master_rw,ack,rep_start,inter_rst,halt;
wire prescale_reg_en;
wire ctr_reg_en;
wire sr_reg_en;
wire to_reg_en;
wire addr_reg_en;
wire dr_reg_en;
reg [7:0]data_out,sr_reg,ctr_reg,dr_reg,rr_reg;
wire [7:0]data_in;                                                               //if address on add_bus matches with register address then set this high.
wire data_ie;                                                           //this is signal used for enaling the data line in read or write cycle.
wire as_d;                                                              //delay version of address strobe signal for detection of rising and falling edge 
reg as_delay_sig;                                                       //same signal.                                  
wire ds_d;                                                              //delayed version of data strobe.
wire decode;
wire rr_reg_en;
 
reg ds_delay_sig;
 
reg prescale_reg_en_sig;
assign prescale_reg_en = prescale_reg_en_sig;
 
reg ctr_reg_en_sig;
assign ctr_reg_en = ctr_reg_en_sig;
 
reg sr_reg_en_sig;
assign sr_reg_en = sr_reg_en_sig;
 
reg to_reg_en_sig;
assign to_reg_en = to_reg_en_sig;
 
reg addr_reg_en_sig;
assign addr_reg_en = addr_reg_en_sig;
 
reg dr_reg_en_sig;
assign dr_reg_en = dr_reg_en_sig;
 
reg as_d_sig;
assign  as_d =  as_d_sig;
 
reg ds_d_sig;
assign ds_d = ds_d_sig;
 
reg data_ie_sig;
assign data_ie = data_ie_sig;
 
//reg core_en_sig;
//assign core_en = core_en_sig;
 
//reg inter_en_sig;
//assign inter_en = inter_en_sig;
 
//reg mode_sig;
//assign mode = mode_sig;
 
//reg master_rw_sig;
//assign master_rw = master_rw_sig;
 
//reg ack_sig;
//assign ack = ack_sig;
 
//reg rep_start_sig;
//assign rep_start = rep_start_sig;
 
reg [7:0]data_sig;
assign data = dr_reg;
 
reg [7:0]prescale_sig;
assign prescale = prescale_sig;
 
reg [7:0]time_out_sig;
assign time_out_reg = time_out_sig;
 
reg [7:0]slave_add_sig;
assign slave_add = slave_add_sig;
 
//reg [7:0]data_out_sig;
//assign data_out = data_out_sig;
 
reg decode_sig;
assign decode = decode_sig;
 
//reg inter_rst_sig;
//assign inter_rst = inter_rst_sig;
 
//reg halt_sig;
//assign halt = halt_sig;
assign data_en = dr_reg_en_sig;
 
reg rr_reg_en_sig;
assign rr_reg_en = rr_reg_en_sig;
 
 
 
assign                  core_en         =       ctr_reg [7];
assign                  inter_en        =       ctr_reg [6];
assign                  mode            =       ctr_reg [5];
assign                  master_rw       =       ctr_reg [4];
assign                  ack             =       ctr_reg [3];
assign                  rep_start       =       ctr_reg [2];
assign                  inter_rst       =       ctr_reg [1];
assign                  halt            =       ctr_reg [0];
 
 
 
 
 
 
//generating delayed version of inputs for detection of rising and falling edge.
//////////////////////////////////////////////////////////////////////////////
 
always@(posedge clk or posedge rst)
begin
 
if(rst)
begin
        as_delay_sig<=1'b0;
        as_d_sig<=1'b0;
        ds_delay_sig<=1'b0;
        ds_d_sig<=1'b0;
end
 
else
begin
        as_delay_sig<=as;
        as_d_sig<=as_delay_sig;
        ds_delay_sig<=ds;
        ds_d_sig<=ds_delay_sig;
end
end
 
always@(posedge clk or posedge rst)
begin
        if(rst)
                decode_sig<=1'b0;
        else if(!as_d && as)
                decode_sig<=1'b1;
        //else
                //decode_sig<=1'b0;
end
 
//address decoding logic
///////////////////////
 
//always@(posedge clk or posedge rst)
always@(rst or as or add_bus or posedge time_rst)
begin
 
if(rst || time_rst)
begin
prescale_reg_en_sig<=1'b0;
ctr_reg_en_sig<=1'b0;
sr_reg_en_sig<=1'b0;
to_reg_en_sig<=1'b0;
addr_reg_en_sig<=1'b0;
dr_reg_en_sig<=1'b0;
rr_reg_en_sig <= 1'b0;
 
//add_match_sig<=1'b0;
end
 
 
 
else if(as)
begin
                if(add_bus == `PRER)
                begin
                        rr_reg_en_sig <= 1'b0;
                        prescale_reg_en_sig<=1'b1;
                        ctr_reg_en_sig<=1'b0;
                        sr_reg_en_sig<=1'b0;
                        to_reg_en_sig<=1'b0;
                        addr_reg_en_sig<=1'b0;
                        dr_reg_en_sig<=1'b0;
                        //add_match_sig<=1'b1;
                end
 
                else if(add_bus == `CTR)
                begin
                        rr_reg_en_sig <= 1'b0;
                        prescale_reg_en_sig<=1'b0;
                        ctr_reg_en_sig<=1'b1;
                        sr_reg_en_sig<=1'b0;
                        to_reg_en_sig<=1'b0;
                        addr_reg_en_sig<=1'b0;
                        dr_reg_en_sig<=1'b0;
                        //add_match_sig<=1'b1;
                end
 
                else if(add_bus == `SR)
                begin
                        rr_reg_en_sig <= 1'b0;
                        prescale_reg_en_sig<=1'b0;
                        ctr_reg_en_sig<=1'b0;
                        sr_reg_en_sig<=1'b1;
                        to_reg_en_sig<=1'b0;
                        addr_reg_en_sig<=1'b0;
                        dr_reg_en_sig<=1'b0;
                        //add_match_sig<=1'b1;
                end
 
                else if(add_bus == `TO)
                begin
                        rr_reg_en_sig <= 1'b0;
                        prescale_reg_en_sig<=1'b0;
                        ctr_reg_en_sig<=1'b0;
                        sr_reg_en_sig<=1'b0;
                        to_reg_en_sig<=1'b1;
                        addr_reg_en_sig<=1'b0;
                        dr_reg_en_sig<=1'b0;
                        //add_match_sig<=1'b1;
                end
 
                else if(add_bus == `ADDR)
                begin
                        rr_reg_en_sig <= 1'b0;
                        prescale_reg_en_sig<=1'b0;
                        ctr_reg_en_sig<=1'b0;
                        sr_reg_en_sig<=1'b0;
                        to_reg_en_sig<=1'b0;
                        addr_reg_en_sig<=1'b1;
                        dr_reg_en_sig<=1'b0;
                        //add_match_sig<=1'b1;
                end
 
                else if(add_bus == `DR)
                begin
 
                        prescale_reg_en_sig<=1'b0;
                        ctr_reg_en_sig<=1'b0;
                        sr_reg_en_sig<=1'b0;
                        to_reg_en_sig<=1'b0;
                        addr_reg_en_sig<=1'b0;
                        dr_reg_en_sig<=1'b1;
                        rr_reg_en_sig <= 1'b0;
                        //add_match_sig<=1'b1;
                end
 
                else if(add_bus == `RR)
                begin
                        rr_reg_en_sig <= 1'b1;
                        prescale_reg_en_sig<=1'b0;
                        ctr_reg_en_sig<=1'b0;
                        sr_reg_en_sig<=1'b0;
                        to_reg_en_sig<=1'b0;
                        addr_reg_en_sig<=1'b0;
                        dr_reg_en_sig<=1'b0;
                        //add_match_sig<=1'b1;
                end
 
                else
                begin
                        rr_reg_en_sig <= 1'b0;
                        prescale_reg_en_sig<=1'b0;
                        ctr_reg_en_sig<=1'b0;
                        sr_reg_en_sig<=1'b0;
                        to_reg_en_sig<=1'b0;
                        addr_reg_en_sig<=1'b0;
                        dr_reg_en_sig<=1'b0;
                        //add_match_sig<=1'b0;
                end
 
 
end
else
begin
                        prescale_reg_en_sig<=1'b0;
                        ctr_reg_en_sig<=1'b0;
                        sr_reg_en_sig<=1'b0;
                        to_reg_en_sig<=1'b0;
                        addr_reg_en_sig<=1'b0;
                        dr_reg_en_sig<=1'b0;
                        rr_reg_en_sig <= 1'b0;
        end
 
end
 
//assigning value of data_ie line
//////////////////////////////////
always@(posedge clk or posedge rst)
begin
        if(rst)
                data_ie_sig<=1'b0;
        else if(!ds_d && ds)
                data_ie_sig<=1'b1;
 
end
 
 
//read data to/from the register specified by processor addrress.
 
 
//always@(rst or addr_reg_en or ctr_reg_en or dr_reg_en or sr_reg_en or prescale_reg_en or to_reg_en or data_ie or rw or data_in )
 
always@(posedge clk or posedge rst)
begin
if(rst)
begin
        sr_reg <= 8'b0;
        dr_reg <= 8'b0;
        rr_reg <= 8'b0;
//ctr_reg <= 8'b0;
end
 
/*else if(ctr_reg_en)
begin
        //sr_reg <= {byte_trans,slave_addressed,bus_busy,arb_lost,time_out,slave_rw,inter,ack_rec};
        ctr_reg <= data_in;
end*/
else
begin
                sr_reg <= {byte_trans,slave_addressed,bus_busy,arb_lost,time_out,slave_rw,inter,ack_rec};
                rr_reg <= i2c_data;
end
end
 
always@(posedge clk or posedge rst or posedge time_rst)
begin
        if(rst || time_rst)
        begin
                //initializing control register
                ctr_reg <= 8'b0;
                /*core_en_sig <= 1'b0;
                inter_en_sig <= 1'b0;
                mode_sig <= 1'b0;
                master_rw_sig <= 1'b0;
                ack_sig <= 1'b0;
                rep_start_sig <= 1'b0;
                inter_rst_sig<=1'b0;*/
                //initializing data and timer register
                data_sig <= 8'b00000000;
                prescale_sig <= 8'b00000000;
                time_out_sig <= 8'b00000000;
                data_out     <= 8'b00000000;
        end
 
        else if (data_ie)
        begin
                //address register
                if(addr_reg_en)                                         //if address matches with slave address register
                begin
                  if(rw)                                                //processor write cycle
                        slave_add_sig <= {data_in[7:1] , 1'b0};
                  else                                                  //processor read cycle
                        data_out <= slave_add;
                end
 
                //control register
                if(ctr_reg_en)                                          //if address matches with cntrol register
                begin
                  if(rw)                                                //processor write cycle
                  //begin
                        /*core_en_sig           <=      #2      ctr_reg [7];
                        inter_en_sig    <=      #2      ctr_reg [6];
                        mode_sig                <=      #2      ctr_reg [5];
                        master_rw_sig   <=      #2      ctr_reg [4];
                        ack_sig                 <=      #2      ctr_reg [3];
                        rep_start_sig   <=      #2      ctr_reg [2];
                        inter_rst_sig   <=      #2      ctr_reg [1];
                        halt_sig                <=      #2      ctr_reg [0];*/
                  //end
 
                  //else
                        ctr_reg <= data_in;                                                     //processor read cycle
                        else
                        data_out <= ctr_reg;
                end
 
                else if(!byte_trans && bus_busy)
                        ctr_reg[1:0] <= 2'b0;
                //data register
 
                if(dr_reg_en)
                begin
                  if(rw)
                        dr_reg <= data_in;
                  else
                        data_out <= dr_reg;
                end
 
                if(rr_reg_en)
                begin
                        data_out <= rr_reg;
                end
 
                //staus register
 
                if(sr_reg_en)
                begin
                        if(!rw)
                        //begin
                                //if(data_in[0]==1'b0)  
                                //inter_rst_sig <= 1'b0;
                                //else
                                //inter_rst_sig <= 1'b1;
                        //end   
                        //else
                        //begin
                                data_out <= sr_reg;
                                //inter_rst_sig<=1'b0;
                        //end
                        //else
                                //inter_rst_sig<=1'b0;
 
                end
 
 
                //prescale register
 
                if(prescale_reg_en)
                begin
                  if(rw)
                        prescale_sig <= data_in;
                  else
                        data_out <= prescale;
                end
 
                //time_out register
 
                if(to_reg_en)
                begin
                  if(rw)
                        time_out_sig <= data_in;
                  else
                        data_out <= time_out_reg;
                end
        end
end
 
//assigning values to bidirectional bus
//////////////////////////////////////
 
//assign data_bus = (!rw && data_ie) ? data_out : 8'bzzzzzzzz;
//assign data_in  = (rw)  ? data_bus : 8'bzzzzzzzz;
 
//interuupt pin to processor
assign irq = (inter && inter_en) ? 1'b1 : 1'b0;
endmodule
 
 
 
 
 
 
 
 
 
 

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Subversion Repositories i2c_master_slave_core

[/] [i2c_master_slave_core/] [trunk/] [i2c_master_slave_core/] [verilog/] [rtl/] [controller_interface.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	toomuch	`////////////////////////////////////////////controller_interface.v////////////////////////////////////////`
2			`// //`
3			`//Design Engineer: Ravi Gupta //`
4			`//Company Name : Toomuch Semiconductor`
5			`//Email : ravi1.gupta@toomuchsemi.com //`
6			`// //`
7			`//Purpose : This core will be used as an interface between I2C core and Processor //`
8			`//Created : 6-12-2007 //`
9			`// //`
10			`// //`
11			`// //`
12			`// //`
13			`// //`
14			`// //`
15			`// //`
16			`// //`
17			`//Modification : Change the control register,added halt reset and inter_rst in control register`
18			`/////////////////////////////////////////////////////////////////////////////////////////////////////////`
19
20			`/*// synopsys translate_off`
21			`include "oc8051_timescale.v"
22			`// synopsys translate_on`
23
24			`include "oc8051_defines.v"*/
25
26
27			`module processor_interface (clk,rst,add_bus,data_in,data_out,as,ds,rw,bus_busy,byte_trans,slave_addressed,arb_lost,slave_rw,inter,ack_rec,`
28			`core_en,inter_en,mode,master_rw,ack,rep_start,data,i2c_data,slave_add,time_out_reg,prescale,irq,time_out,inter_rst,halt,data_en,time_rst);`
29			`input clk; //System clock`
30			`input rst; //system reset`
31
32			`//signals connecting core to processor`
33			`/////////////////////////////////////`
34
35			`input [7:0]add_bus; //contains address of internal register`
36			`input [7:0]data_in; //trnasport the data for i2c core`
37			`input as; //asserted high indicates vallid address has been placed on the address bus`
38			`input ds; //asserted high indicates valid data on data bus`
39			`input rw; //"1" indicates that processor has to write else read`
40			`output irq; //interrupt to processor`
41			`output inter_rst; //this bit will be written by processor when it will clear the interrupt.`
42			`output [7:0]data_out;`
43			`output halt;`
44			`output data_en;`
45			`input time_rst;`
46
47			`//signals from core to reflect te status of core and buses`
48			`///////////////////////////////////////////////////////////`
49
50			`input bus_busy; //signal from core indicates bus is busy`
51			`input byte_trans; //signal from core indicates byte transfer is in progress`
52			`input slave_addressed; //signal from core indicares core has been identified as slave`
53			`input arb_lost; //signal from core indicates bus error`
54			`input slave_rw; //signal from core indicates operation of slave core`
55			`input inter; //signal from core.this will interrupt the processor if this bit as well as interrupt enable is high`
56			`input ack_rec; //signal from core to reflect the status of ack bit`
57			`input time_out;`
58
59			`//bits of control register`
60			`//////////////////////////`
61
62			`inout core_en; //this bit must be cleared before any other bit of control register have any effect on core`
63			`inout inter_en; //To intrrupt the core this bit must be set when interrupt is pending`
64			`inout mode; //Transaction from "0" to "1" directes core to act as master else slave`
65			`inout master_rw; //set directiion for master either to transmit or receive`
66			`inout ack; //value of acknowledgment bit to be transmitted on SDA line during ack cycle`
67			`inout rep_start; //set this bit if processor wants a repeated start`
68
69			`//data register`
70			`////////////////`
71
72			`inout [7:0]prescale; //contains the value for generating SCL frequency`
73			`inout [7:0]time_out_reg; //contains the value for maximum low period for scl`
74			`inout [7:0]slave_add; //this is the programmble slave address`
75			`inout [7:0]data; //data for i2c core`
76			`input [7:0]i2c_data; //data from core for processor`
77
78			`//defining registers addresses`
79			`/////////////////////////////`
80
81			`define PRER 8'b0000_0010
82			`define CTR 8'b0000_0100
83			`define SR 8'b0000_1000
84			`define TO 8'b0000_1010
85			`define ADDR 8'b0000_1100
86			`define DR 8'b0000_1110
87			`define RR 8'b0000_0000
88
89			`/*//defing the machine state`
90			`//////////////////////////`
91
92			`parameter processor_idle=2'b00;`
93			`parameter processor_address=2'b01;`
94			`parameter processor_data=2'b10;`
95			`parameter processor_ack=2'b11;*/`
96
97			`//Definig internal registers and wires`
98			`/////////////////////////////////////`
99
100			`wire core_en,inter_en,mode,master_rw,ack,rep_start,inter_rst,halt;`
101			`wire prescale_reg_en;`
102			`wire ctr_reg_en;`
103			`wire sr_reg_en;`
104			`wire to_reg_en;`
105			`wire addr_reg_en;`
106			`wire dr_reg_en;`
107			`reg [7:0]data_out,sr_reg,ctr_reg,dr_reg,rr_reg;`
108			`wire [7:0]data_in; //if address on add_bus matches with register address then set this high.`
109			`wire data_ie; //this is signal used for enaling the data line in read or write cycle.`
110			`wire as_d; //delay version of address strobe signal for detection of rising and falling edge`
111			`reg as_delay_sig; //same signal.`
112			`wire ds_d; //delayed version of data strobe.`
113			`wire decode;`
114			`wire rr_reg_en;`
115
116			`reg ds_delay_sig;`
117
118			`reg prescale_reg_en_sig;`
119			`assign prescale_reg_en = prescale_reg_en_sig;`
120
121			`reg ctr_reg_en_sig;`
122			`assign ctr_reg_en = ctr_reg_en_sig;`
123
124			`reg sr_reg_en_sig;`
125			`assign sr_reg_en = sr_reg_en_sig;`
126
127			`reg to_reg_en_sig;`
128			`assign to_reg_en = to_reg_en_sig;`
129
130			`reg addr_reg_en_sig;`
131			`assign addr_reg_en = addr_reg_en_sig;`
132
133			`reg dr_reg_en_sig;`
134			`assign dr_reg_en = dr_reg_en_sig;`
135
136			`reg as_d_sig;`
137			`assign as_d = as_d_sig;`
138
139			`reg ds_d_sig;`
140			`assign ds_d = ds_d_sig;`
141
142			`reg data_ie_sig;`
143			`assign data_ie = data_ie_sig;`
144
145			`//reg core_en_sig;`
146			`//assign core_en = core_en_sig;`
147
148			`//reg inter_en_sig;`
149			`//assign inter_en = inter_en_sig;`
150
151			`//reg mode_sig;`
152			`//assign mode = mode_sig;`
153
154			`//reg master_rw_sig;`
155			`//assign master_rw = master_rw_sig;`
156
157			`//reg ack_sig;`
158			`//assign ack = ack_sig;`
159
160			`//reg rep_start_sig;`
161			`//assign rep_start = rep_start_sig;`
162
163			`reg [7:0]data_sig;`
164			`assign data = dr_reg;`
165
166			`reg [7:0]prescale_sig;`
167			`assign prescale = prescale_sig;`
168
169			`reg [7:0]time_out_sig;`
170			`assign time_out_reg = time_out_sig;`
171
172			`reg [7:0]slave_add_sig;`
173			`assign slave_add = slave_add_sig;`
174
175			`//reg [7:0]data_out_sig;`
176			`//assign data_out = data_out_sig;`
177
178			`reg decode_sig;`
179			`assign decode = decode_sig;`
180
181			`//reg inter_rst_sig;`
182			`//assign inter_rst = inter_rst_sig;`
183
184			`//reg halt_sig;`
185			`//assign halt = halt_sig;`
186			`assign data_en = dr_reg_en_sig;`
187
188			`reg rr_reg_en_sig;`
189			`assign rr_reg_en = rr_reg_en_sig;`
190
191
192
193			`assign core_en = ctr_reg [7];`
194			`assign inter_en = ctr_reg [6];`
195			`assign mode = ctr_reg [5];`
196			`assign master_rw = ctr_reg [4];`
197			`assign ack = ctr_reg [3];`
198			`assign rep_start = ctr_reg [2];`
199			`assign inter_rst = ctr_reg [1];`
200			`assign halt = ctr_reg [0];`
201
202
203
204
205
206
207			`//generating delayed version of inputs for detection of rising and falling edge.`
208			`//////////////////////////////////////////////////////////////////////////////`
209
210			`always@(posedge clk or posedge rst)`
211			`begin`
212
213			`if(rst)`
214			`begin`
215			`as_delay_sig<=1'b0;`
216			`as_d_sig<=1'b0;`
217			`ds_delay_sig<=1'b0;`
218			`ds_d_sig<=1'b0;`
219			`end`
220
221			`else`
222			`begin`
223			`as_delay_sig<=as;`
224			`as_d_sig<=as_delay_sig;`
225			`ds_delay_sig<=ds;`
226			`ds_d_sig<=ds_delay_sig;`
227			`end`
228			`end`
229
230			`always@(posedge clk or posedge rst)`
231			`begin`
232			`if(rst)`
233			`decode_sig<=1'b0;`
234			`else if(!as_d && as)`
235			`decode_sig<=1'b1;`
236			`//else`
237			`//decode_sig<=1'b0;`
238			`end`
239
240			`//address decoding logic`
241			`///////////////////////`
242
243			`//always@(posedge clk or posedge rst)`
244			`always@(rst or as or add_bus or posedge time_rst)`
245			`begin`
246
247			`if(rst \|\| time_rst)`
248			`begin`
249			`prescale_reg_en_sig<=1'b0;`
250			`ctr_reg_en_sig<=1'b0;`
251			`sr_reg_en_sig<=1'b0;`
252			`to_reg_en_sig<=1'b0;`
253			`addr_reg_en_sig<=1'b0;`
254			`dr_reg_en_sig<=1'b0;`
255			`rr_reg_en_sig <= 1'b0;`
256
257			`//add_match_sig<=1'b0;`
258			`end`
259
260
261
262			`else if(as)`
263			`begin`
264			if(add_bus == `PRER)
265			`begin`
266			`rr_reg_en_sig <= 1'b0;`
267			`prescale_reg_en_sig<=1'b1;`
268			`ctr_reg_en_sig<=1'b0;`
269			`sr_reg_en_sig<=1'b0;`
270			`to_reg_en_sig<=1'b0;`
271			`addr_reg_en_sig<=1'b0;`
272			`dr_reg_en_sig<=1'b0;`
273			`//add_match_sig<=1'b1;`
274			`end`
275
276			else if(add_bus == `CTR)
277			`begin`
278			`rr_reg_en_sig <= 1'b0;`
279			`prescale_reg_en_sig<=1'b0;`
280			`ctr_reg_en_sig<=1'b1;`
281			`sr_reg_en_sig<=1'b0;`
282			`to_reg_en_sig<=1'b0;`
283			`addr_reg_en_sig<=1'b0;`
284			`dr_reg_en_sig<=1'b0;`
285			`//add_match_sig<=1'b1;`
286			`end`
287
288			else if(add_bus == `SR)
289			`begin`
290			`rr_reg_en_sig <= 1'b0;`
291			`prescale_reg_en_sig<=1'b0;`
292			`ctr_reg_en_sig<=1'b0;`
293			`sr_reg_en_sig<=1'b1;`
294			`to_reg_en_sig<=1'b0;`
295			`addr_reg_en_sig<=1'b0;`
296			`dr_reg_en_sig<=1'b0;`
297			`//add_match_sig<=1'b1;`
298			`end`
299
300			else if(add_bus == `TO)
301			`begin`
302			`rr_reg_en_sig <= 1'b0;`
303			`prescale_reg_en_sig<=1'b0;`
304			`ctr_reg_en_sig<=1'b0;`
305			`sr_reg_en_sig<=1'b0;`
306			`to_reg_en_sig<=1'b1;`
307			`addr_reg_en_sig<=1'b0;`
308			`dr_reg_en_sig<=1'b0;`
309			`//add_match_sig<=1'b1;`
310			`end`
311
312			else if(add_bus == `ADDR)
313			`begin`
314			`rr_reg_en_sig <= 1'b0;`
315			`prescale_reg_en_sig<=1'b0;`
316			`ctr_reg_en_sig<=1'b0;`
317			`sr_reg_en_sig<=1'b0;`
318			`to_reg_en_sig<=1'b0;`
319			`addr_reg_en_sig<=1'b1;`
320			`dr_reg_en_sig<=1'b0;`
321			`//add_match_sig<=1'b1;`
322			`end`
323
324			else if(add_bus == `DR)
325			`begin`
326
327			`prescale_reg_en_sig<=1'b0;`
328			`ctr_reg_en_sig<=1'b0;`
329			`sr_reg_en_sig<=1'b0;`
330			`to_reg_en_sig<=1'b0;`
331			`addr_reg_en_sig<=1'b0;`
332			`dr_reg_en_sig<=1'b1;`
333			`rr_reg_en_sig <= 1'b0;`
334			`//add_match_sig<=1'b1;`
335			`end`
336
337			else if(add_bus == `RR)
338			`begin`
339			`rr_reg_en_sig <= 1'b1;`
340			`prescale_reg_en_sig<=1'b0;`
341			`ctr_reg_en_sig<=1'b0;`
342			`sr_reg_en_sig<=1'b0;`
343			`to_reg_en_sig<=1'b0;`
344			`addr_reg_en_sig<=1'b0;`
345			`dr_reg_en_sig<=1'b0;`
346			`//add_match_sig<=1'b1;`
347			`end`
348
349			`else`
350			`begin`
351			`rr_reg_en_sig <= 1'b0;`
352			`prescale_reg_en_sig<=1'b0;`
353			`ctr_reg_en_sig<=1'b0;`
354			`sr_reg_en_sig<=1'b0;`
355			`to_reg_en_sig<=1'b0;`
356			`addr_reg_en_sig<=1'b0;`
357			`dr_reg_en_sig<=1'b0;`
358			`//add_match_sig<=1'b0;`
359			`end`
360
361
362			`end`
363			`else`
364			`begin`
365			`prescale_reg_en_sig<=1'b0;`
366			`ctr_reg_en_sig<=1'b0;`
367			`sr_reg_en_sig<=1'b0;`
368			`to_reg_en_sig<=1'b0;`
369			`addr_reg_en_sig<=1'b0;`
370			`dr_reg_en_sig<=1'b0;`
371			`rr_reg_en_sig <= 1'b0;`
372			`end`
373
374			`end`
375
376			`//assigning value of data_ie line`
377			`//////////////////////////////////`
378			`always@(posedge clk or posedge rst)`
379			`begin`
380			`if(rst)`
381			`data_ie_sig<=1'b0;`
382			`else if(!ds_d && ds)`
383			`data_ie_sig<=1'b1;`
384
385			`end`
386
387
388			`//read data to/from the register specified by processor addrress.`
389
390
391			`//always@(rst or addr_reg_en or ctr_reg_en or dr_reg_en or sr_reg_en or prescale_reg_en or to_reg_en or data_ie or rw or data_in )`
392
393			`always@(posedge clk or posedge rst)`
394			`begin`
395			`if(rst)`
396			`begin`
397			`sr_reg <= 8'b0;`
398			`dr_reg <= 8'b0;`
399			`rr_reg <= 8'b0;`
400			`//ctr_reg <= 8'b0;`
401			`end`
402
403			`/*else if(ctr_reg_en)`
404			`begin`
405			`//sr_reg <= {byte_trans,slave_addressed,bus_busy,arb_lost,time_out,slave_rw,inter,ack_rec};`
406			`ctr_reg <= data_in;`
407			`end*/`
408			`else`
409			`begin`
410			`sr_reg <= {byte_trans,slave_addressed,bus_busy,arb_lost,time_out,slave_rw,inter,ack_rec};`
411			`rr_reg <= i2c_data;`
412			`end`
413			`end`
414
415			`always@(posedge clk or posedge rst or posedge time_rst)`
416			`begin`
417			`if(rst \|\| time_rst)`
418			`begin`
419			`//initializing control register`
420			`ctr_reg <= 8'b0;`
421			`/*core_en_sig <= 1'b0;`
422			`inter_en_sig <= 1'b0;`
423			`mode_sig <= 1'b0;`
424			`master_rw_sig <= 1'b0;`
425			`ack_sig <= 1'b0;`
426			`rep_start_sig <= 1'b0;`
427			`inter_rst_sig<=1'b0;*/`
428			`//initializing data and timer register`
429			`data_sig <= 8'b00000000;`
430			`prescale_sig <= 8'b00000000;`
431			`time_out_sig <= 8'b00000000;`
432			`data_out <= 8'b00000000;`
433			`end`
434
435			`else if (data_ie)`
436			`begin`
437			`//address register`
438			`if(addr_reg_en) //if address matches with slave address register`
439			`begin`
440			`if(rw) //processor write cycle`
441			`slave_add_sig <= {data_in[7:1] , 1'b0};`
442			`else //processor read cycle`
443			`data_out <= slave_add;`
444			`end`
445
446			`//control register`
447			`if(ctr_reg_en) //if address matches with cntrol register`
448			`begin`
449			`if(rw) //processor write cycle`
450			`//begin`
451			`/*core_en_sig <= #2 ctr_reg [7];`
452			`inter_en_sig <= #2 ctr_reg [6];`
453			`mode_sig <= #2 ctr_reg [5];`
454			`master_rw_sig <= #2 ctr_reg [4];`
455			`ack_sig <= #2 ctr_reg [3];`
456			`rep_start_sig <= #2 ctr_reg [2];`
457			`inter_rst_sig <= #2 ctr_reg [1];`
458			`halt_sig <= #2 ctr_reg [0];*/`
459			`//end`
460
461			`//else`
462			`ctr_reg <= data_in; //processor read cycle`
463			`else`
464			`data_out <= ctr_reg;`
465			`end`
466
467			`else if(!byte_trans && bus_busy)`
468			`ctr_reg[1:0] <= 2'b0;`
469			`//data register`
470
471			`if(dr_reg_en)`
472			`begin`
473			`if(rw)`
474			`dr_reg <= data_in;`
475			`else`
476			`data_out <= dr_reg;`
477			`end`
478
479			`if(rr_reg_en)`
480			`begin`
481			`data_out <= rr_reg;`
482			`end`
483
484			`//staus register`
485
486			`if(sr_reg_en)`
487			`begin`
488			`if(!rw)`
489			`//begin`
490			`//if(data_in[0]==1'b0)`
491			`//inter_rst_sig <= 1'b0;`
492			`//else`
493			`//inter_rst_sig <= 1'b1;`
494			`//end`
495			`//else`
496			`//begin`
497			`data_out <= sr_reg;`
498			`//inter_rst_sig<=1'b0;`
499			`//end`
500			`//else`
501			`//inter_rst_sig<=1'b0;`
502
503			`end`
504
505
506			`//prescale register`
507
508			`if(prescale_reg_en)`
509			`begin`
510			`if(rw)`
511			`prescale_sig <= data_in;`
512			`else`
513			`data_out <= prescale;`
514			`end`
515
516			`//time_out register`
517
518			`if(to_reg_en)`
519			`begin`
520			`if(rw)`
521			`time_out_sig <= data_in;`
522			`else`
523			`data_out <= time_out_reg;`
524			`end`
525			`end`
526			`end`
527
528			`//assigning values to bidirectional bus`
529			`//////////////////////////////////////`
530
531			`//assign data_bus = (!rw && data_ie) ? data_out : 8'bzzzzzzzz;`
532			`//assign data_in = (rw) ? data_bus : 8'bzzzzzzzz;`
533
534			`//interuupt pin to processor`
535			`assign irq = (inter && inter_en) ? 1'b1 : 1'b0;`
536			`endmodule`
537
538
539
540
541
542
543
544
545
546