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toomuch |
//////////////////////////////////////////////////////////////////////////////////////////
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//Design Engineer: Ravi Gupta //
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//Company Name : Toomuch Semiconductor
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//Email : ravi1.gupta@toomuchsemi.com //
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// //
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// //
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//Purpose : This module will simply interconnect controller interface // //
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// controller_interface with ms_core. //
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// //
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// //
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//Date : 11-12-07 //
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// //
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// //
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// //
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// //
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// //
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// //
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// //
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//////////////////////////////////////////////////////////////////////////////////////////
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/*// synopsys translate_off
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`include "oc8051_timescale.v"
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// synopsys translate_on
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`include "oc8051_defines.v"*/
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module block(scl_oe,scl_in,scl_o,sda_oe,sda_in,sda_o,wb_add_i,wb_data_i,wb_data_o,wb_we_i,wb_stb_i,wb_cyc_i,irq,trans_comp,wb_clk_i,wb_rst_i,wb_ack_o);
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//inout scl; //Bi-directional lines to follow i2c protocol for data transfer.
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input sda_in; //sda input
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output sda_oe; //control line for bidirectional buffer
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output sda_o; //input line for bi_firectional buffer
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input scl_in;
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output scl_o;
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output scl_oe;
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input [7:0]wb_data_i; //Bi-direction buses for transfering data to/from processor.
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input [7:0]wb_add_i; //Transfer the addresses of intenal registers.
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input wb_we_i; //signal from processor to indicate whether its a read or write cycle.
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input wb_stb_i; //when asserted indicates address is valid.
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input wb_cyc_i; //when asserted indicates data is valid.
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output irq; //interupt signal to processor.
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input wb_clk_i; //system clock.
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input wb_rst_i; //asynchrnous reset active high.
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inout trans_comp; //temprory signal for testing the core
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output [7:0]wb_data_o;
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output wb_ack_o;
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//declaratiion of internal signals
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//////////////////////////////////
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// control register
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wire [7:0] slave_add; // I2C address
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wire arb_lost; // indicates that arbitration for the i2c bus is lost
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wire bus_busy; // indicates the i2c bus is busy
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wire [7:0] i2c_up; // i2c data register
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wire [7:0] data; // uC data register
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wire core_en; // i2c enable - used as i2c reset
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wire inter_en; // interrupt enable
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wire inter; // interrupt pending
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wire mode; // i2c master/slave select
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wire master_rw; // master read/write
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wire rep_start; // generate a repeated start
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wire ack_rec; // value of received acknowledge
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wire slave_rw; // slave read/write
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wire ack; // value of acknowledge to be transmitted
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wire byte_trans; // indicates that one byte of data is being transferred
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wire slave_addressed; // address of core matches with address transferred
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wire time_out; // max low period for SCL has excedded
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wire [7:0]time_out_reg; // programmable max time for SCL low period
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wire [7:0]prescale;
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wire inter_rst;
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wire [7:0]wb_data_o;
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wire halt;
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wire data_en;
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wire time_rst;
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reg wb_ack_o;
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wire rst;
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assign trans_comp = byte_trans;
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always@(posedge wb_clk_i)
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begin
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wb_ack_o <= #1 wb_stb_i & wb_cyc_i & ~wb_ack_o;
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end
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//port map for i2c controller
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////////////////////////////
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core i2c_core
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(
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.clk(wb_clk_i),
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.rst(core_en),
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.sda_oe(sda_oe),
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.sda_in(sda_in),
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.sda_o(sda_o),
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.scl_oe(scl_oe),
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.scl_o(scl_o),
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.scl_in(scl_in),
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.ack(ack),
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.mode(mode),
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.rep_start(rep_start),
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.master_rw(master_rw),
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.data_in(data[7:0]),
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.slave_add(slave_add[7:0]),
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.bus_busy(bus_busy),
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.byte_trans(byte_trans),
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.slave_addressed(slave_addressed),
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.arb_lost(arb_lost),
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.slave_rw(slave_rw),
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.time_out(time_out),
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.inter(inter),
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.ack_rec(ack_rec),
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.i2c_up(i2c_up[7:0]),
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.time_out_reg(time_out_reg[7:0]),
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.prescale_reg(prescale[7:0]),
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.inter_en(inter_en),
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.inter_rst(inter_rst),
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.data_en(data_en),
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.halt_rst(halt),
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.h_rst(wb_rst_i),
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.time_rst(time_rst));
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//port map for controller interface
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///////////////////////////////////
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processor_interface processor_interface
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(
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.clk(wb_clk_i),
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.rst(wb_rst_i),
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.add_bus(wb_add_i[7:0]),
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.data_in(wb_data_i[7:0]),
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.as(wb_stb_i),
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.ds(wb_cyc_i),
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.rw(wb_we_i),
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.bus_busy(bus_busy),
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.byte_trans(byte_trans),
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.slave_addressed(slave_addressed),
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.arb_lost(arb_lost),
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.slave_rw(slave_rw),
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.inter(inter),
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.ack_rec(ack_rec),
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.core_en(core_en),
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.inter_en(inter_en),
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.mode(mode),
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.master_rw(master_rw),
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.ack(ack),
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.rep_start(rep_start),
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.data(data[7:0]),
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.i2c_data(i2c_up[7:0]),
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.slave_add(slave_add),
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.time_out_reg(time_out_reg[7:0]),
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.prescale(prescale[7:0]),
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.irq(irq),
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.time_out(time_out),
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.inter_rst(inter_rst),
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.halt(halt),
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.data_en(data_en),
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.time_rst(time_rst),
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.data_out(wb_data_o));
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//always@(scl or sda)
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//$display($time,"scl=%b\tsda=%b\t\n",scl,sda);
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endmodule
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