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[/] [i2c_to_wb/] [trunk/] [src/] [i2c_to_wb_fsm.v] - Blame information for rev 3

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// --------------------------------------------------------------------
//
// --------------------------------------------------------------------
 
 
`include "timescale.v"
 
 
module
  i2c_to_wb_fsm
  (
    input         i2c_data,
    input         i2c_data_rise,
    input         i2c_data_fall,
 
    input         i2c_clk,
    input         i2c_clk_rise,
    input         i2c_clk_fall,
 
    input         i2c_bit_7,
    output        i2c_ack_done,
 
    output        tip_addr_byte,
//     output        tip_byte, 
    output        tip_read_byte,
    output        tip_write_byte,
    output        tip_wr_ack,
    output        tip_rd_ack,
    output        tip_addr_ack,
//     output        tip_ack, 
//     output        tip_write, 
//     output        tip_read, 
 
    output  [7:0] state_out,
 
    input         wb_clk_i,
    input         wb_rst_i
  );
 
  // --------------------------------------------------------------------
  //  wires
  wire xmt_byte_done;
 
//   wire i2c_read  = 1'b0;
//   wire i2c_ack_done;
  wire i2c_address_hit = 1'b1;
 
  wire tip_ack;
 
 
  // --------------------------------------------------------------------
  //  start & stop 
 
  wire start_detected = i2c_data_fall & i2c_clk;
  wire stop_detected  = i2c_data_rise & i2c_clk;
 
 
  // --------------------------------------------------------------------
  //  state machine
 
  localparam   STATE_IDLE       = 8'b00000001;
  localparam   STATE_ADDR_BYTE  = 8'b00000010;
  localparam   STATE_ADDR_ACK   = 8'b00000100;
  localparam   STATE_WRITE      = 8'b00001000;
  localparam   STATE_WR_ACK     = 8'b00010000;
  localparam   STATE_READ       = 8'b00100000;
  localparam   STATE_RD_ACK     = 8'b01000000;
  localparam   STATE_ERROR      = 8'b10000000;
 
  reg [7:0] state;
  reg [7:0] next_state;
 
  always @(posedge wb_clk_i or posedge wb_rst_i)
    if(wb_rst_i)
      state <= STATE_IDLE;
    else
      state <= next_state;
 
  always @(*)
    case( state )
      STATE_IDLE:       if( start_detected )
                          next_state = STATE_ADDR_BYTE;
                        else
                          next_state = STATE_IDLE;
 
      STATE_ADDR_BYTE:  if( xmt_byte_done )
                          if( i2c_address_hit )
                            next_state = STATE_ADDR_ACK;
                          else
                            next_state = STATE_IDLE;
                        else if( start_detected | stop_detected )
                          next_state = STATE_ERROR;
                        else
                          next_state = STATE_ADDR_BYTE;
 
      STATE_ADDR_ACK:   if( i2c_ack_done )
                          if( i2c_bit_7 )
                            next_state = STATE_READ;
                          else
                            next_state = STATE_WRITE;
                        else if( start_detected | stop_detected )
                          next_state = STATE_ERROR;
                        else
                          next_state = STATE_ADDR_ACK;
 
      STATE_WRITE:      if( xmt_byte_done )
                          next_state = STATE_WR_ACK;
                        else if( start_detected )
                          next_state = STATE_ADDR_BYTE;
                        else if( stop_detected )
                          next_state = STATE_IDLE;
                        else
                          next_state = STATE_WRITE;
 
      STATE_WR_ACK:     if( i2c_ack_done )
                          next_state = STATE_WRITE;
                        else if( start_detected | stop_detected )
                          next_state = STATE_ERROR;
                        else
                          next_state = STATE_WR_ACK;
 
      STATE_READ:       if( xmt_byte_done )
                          next_state = STATE_RD_ACK;
                        else if( start_detected )
                          next_state = STATE_ADDR_BYTE;
                        else if( stop_detected )
                          next_state = STATE_IDLE;
                        else
                          next_state = STATE_READ;
 
      STATE_RD_ACK:     if( i2c_ack_done )
                          next_state = STATE_READ;
                        else if( start_detected | stop_detected )
                          next_state = STATE_ERROR;
                        else
                          next_state = STATE_RD_ACK;
 
      STATE_ERROR:      next_state = STATE_IDLE;
 
      default:          next_state = STATE_ERROR;
    endcase
 
 
  // --------------------------------------------------------------------
  //  bit counter 
  reg [3:0] bit_count;
 
  assign  xmt_byte_done = (bit_count == 4'h7) & i2c_clk_rise;
  assign  tip_ack       = (bit_count == 4'h8);
  assign  i2c_ack_done  = tip_ack & i2c_clk_rise;
 
  always @(posedge wb_clk_i)
    if( wb_rst_i | i2c_ack_done | start_detected )
      bit_count <= 4'hf;
    else if( i2c_clk_fall )
      bit_count <= bit_count + 1;
 
 
// --------------------------------------------------------------------
//  outputs
 
  assign state_out = state;
 
  assign  tip_addr_byte   = (state == STATE_ADDR_BYTE);
  assign  tip_addr_ack    = (state == STATE_ADDR_ACK);
  assign  tip_read_byte   = (state == STATE_READ);
  assign  tip_write_byte  = tip_addr_byte               | (state == STATE_WRITE);
  assign  tip_wr_ack      = tip_addr_ack                | (state == STATE_WR_ACK);
  assign  tip_rd_ack      = (state == STATE_RD_ACK);
//   assign  tip_byte        = tip_write_byte              | tip_read_byte;
//   assign  tip_write       = tip_write_byte              | tip_wr_ack;
//   assign  tip_read        = tip_read_byte               | tip_rd_ack;
 
endmodule
 
 
 

Line No.	Rev	Author	Line
1	3	qaztronic	`// --------------------------------------------------------------------`
2			`//`
3			`// --------------------------------------------------------------------`
4
5
6			`include "timescale.v"
7
8
9			`module`
10			`i2c_to_wb_fsm`
11			`(`
12			`input i2c_data,`
13			`input i2c_data_rise,`
14			`input i2c_data_fall,`
15
16			`input i2c_clk,`
17			`input i2c_clk_rise,`
18			`input i2c_clk_fall,`
19
20			`input i2c_bit_7,`
21			`output i2c_ack_done,`
22
23			`output tip_addr_byte,`
24			`// output tip_byte,`
25			`output tip_read_byte,`
26			`output tip_write_byte,`
27			`output tip_wr_ack,`
28			`output tip_rd_ack,`
29			`output tip_addr_ack,`
30			`// output tip_ack,`
31			`// output tip_write,`
32			`// output tip_read,`
33
34			`output [7:0] state_out,`
35
36			`input wb_clk_i,`
37			`input wb_rst_i`
38			`);`
39
40			`// --------------------------------------------------------------------`
41			`// wires`
42			`wire xmt_byte_done;`
43
44			`// wire i2c_read = 1'b0;`
45			`// wire i2c_ack_done;`
46			`wire i2c_address_hit = 1'b1;`
47
48			`wire tip_ack;`
49
50
51			`// --------------------------------------------------------------------`
52			`// start & stop`
53
54			`wire start_detected = i2c_data_fall & i2c_clk;`
55			`wire stop_detected = i2c_data_rise & i2c_clk;`
56
57
58			`// --------------------------------------------------------------------`
59			`// state machine`
60
61			`localparam STATE_IDLE = 8'b00000001;`
62			`localparam STATE_ADDR_BYTE = 8'b00000010;`
63			`localparam STATE_ADDR_ACK = 8'b00000100;`
64			`localparam STATE_WRITE = 8'b00001000;`
65			`localparam STATE_WR_ACK = 8'b00010000;`
66			`localparam STATE_READ = 8'b00100000;`
67			`localparam STATE_RD_ACK = 8'b01000000;`
68			`localparam STATE_ERROR = 8'b10000000;`
69
70			`reg [7:0] state;`
71			`reg [7:0] next_state;`
72
73			`always @(posedge wb_clk_i or posedge wb_rst_i)`
74			`if(wb_rst_i)`
75			`state <= STATE_IDLE;`
76			`else`
77			`state <= next_state;`
78
79			`always @(*)`
80			`case( state )`
81			`STATE_IDLE: if( start_detected )`
82			`next_state = STATE_ADDR_BYTE;`
83			`else`
84			`next_state = STATE_IDLE;`
85
86			`STATE_ADDR_BYTE: if( xmt_byte_done )`
87			`if( i2c_address_hit )`
88			`next_state = STATE_ADDR_ACK;`
89			`else`
90			`next_state = STATE_IDLE;`
91			`else if( start_detected \| stop_detected )`
92			`next_state = STATE_ERROR;`
93			`else`
94			`next_state = STATE_ADDR_BYTE;`
95
96			`STATE_ADDR_ACK: if( i2c_ack_done )`
97			`if( i2c_bit_7 )`
98			`next_state = STATE_READ;`
99			`else`
100			`next_state = STATE_WRITE;`
101			`else if( start_detected \| stop_detected )`
102			`next_state = STATE_ERROR;`
103			`else`
104			`next_state = STATE_ADDR_ACK;`
105
106			`STATE_WRITE: if( xmt_byte_done )`
107			`next_state = STATE_WR_ACK;`
108			`else if( start_detected )`
109			`next_state = STATE_ADDR_BYTE;`
110			`else if( stop_detected )`
111			`next_state = STATE_IDLE;`
112			`else`
113			`next_state = STATE_WRITE;`
114
115			`STATE_WR_ACK: if( i2c_ack_done )`
116			`next_state = STATE_WRITE;`
117			`else if( start_detected \| stop_detected )`
118			`next_state = STATE_ERROR;`
119			`else`
120			`next_state = STATE_WR_ACK;`
121
122			`STATE_READ: if( xmt_byte_done )`
123			`next_state = STATE_RD_ACK;`
124			`else if( start_detected )`
125			`next_state = STATE_ADDR_BYTE;`
126			`else if( stop_detected )`
127			`next_state = STATE_IDLE;`
128			`else`
129			`next_state = STATE_READ;`
130
131			`STATE_RD_ACK: if( i2c_ack_done )`
132			`next_state = STATE_READ;`
133			`else if( start_detected \| stop_detected )`
134			`next_state = STATE_ERROR;`
135			`else`
136			`next_state = STATE_RD_ACK;`
137
138			`STATE_ERROR: next_state = STATE_IDLE;`
139
140			`default: next_state = STATE_ERROR;`
141			`endcase`
142
143
144			`// --------------------------------------------------------------------`
145			`// bit counter`
146			`reg [3:0] bit_count;`
147
148			`assign xmt_byte_done = (bit_count == 4'h7) & i2c_clk_rise;`
149			`assign tip_ack = (bit_count == 4'h8);`
150			`assign i2c_ack_done = tip_ack & i2c_clk_rise;`
151
152			`always @(posedge wb_clk_i)`
153			`if( wb_rst_i \| i2c_ack_done \| start_detected )`
154			`bit_count <= 4'hf;`
155			`else if( i2c_clk_fall )`
156			`bit_count <= bit_count + 1;`
157
158
159			`// --------------------------------------------------------------------`
160			`// outputs`
161
162			`assign state_out = state;`
163
164			`assign tip_addr_byte = (state == STATE_ADDR_BYTE);`
165			`assign tip_addr_ack = (state == STATE_ADDR_ACK);`
166			`assign tip_read_byte = (state == STATE_READ);`
167			`assign tip_write_byte = tip_addr_byte \| (state == STATE_WRITE);`
168			`assign tip_wr_ack = tip_addr_ack \| (state == STATE_WR_ACK);`
169			`assign tip_rd_ack = (state == STATE_RD_ACK);`
170			`// assign tip_byte = tip_write_byte \| tip_read_byte;`
171			`// assign tip_write = tip_write_byte \| tip_wr_ack;`
172			`// assign tip_read = tip_read_byte \| tip_rd_ack;`
173
174			`endmodule`
175
176
177

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[/] [i2c_to_wb/] [trunk/] [src/] [i2c_to_wb_fsm.v] - Blame information for rev 3