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[/] [i2cslave/] [trunk/] [model/] [i2c_master_byte_ctrl.v] - Blame information for rev 5

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1 2 sfielding
/////////////////////////////////////////////////////////////////////
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////                                                             ////
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////  WISHBONE rev.B2 compliant I2C Master byte-controller       ////
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////                                                             ////
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////                                                             ////
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////  Author: Richard Herveille                                  ////
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////          richard@asics.ws                                   ////
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////          www.asics.ws                                       ////
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////                                                             ////
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////  Downloaded from: http://www.opencores.org/projects/i2c/    ////
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////                                                             ////
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/////////////////////////////////////////////////////////////////////
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////                                                             ////
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//// Copyright (C) 2001 Richard Herveille                        ////
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////                    richard@asics.ws                         ////
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////                                                             ////
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//// This source file may be used and distributed without        ////
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//// restriction provided that this copyright statement is not   ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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////                                                             ////
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////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
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//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
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//// POSSIBILITY OF SUCH DAMAGE.                                 ////
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////                                                             ////
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/////////////////////////////////////////////////////////////////////
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//  CVS Log
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//
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//  $Id: i2c_master_byte_ctrl.v,v 1.1 2008-11-08 13:15:10 sfielding Exp $
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//
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//  $Date: 2008-11-08 13:15:10 $
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//  $Revision: 1.1 $
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//  $Author: sfielding $
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//  $Locker:  $
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//  $State: Exp $
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//
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// Change History:
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//               $Log: not supported by cvs2svn $
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//               Revision 1.7  2004/02/18 11:40:46  rherveille
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//               Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command.
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//
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//               Revision 1.6  2003/08/09 07:01:33  rherveille
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//               Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
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//               Fixed a potential bug in the byte controller's host-acknowledge generation.
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//
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//               Revision 1.5  2002/12/26 15:02:32  rherveille
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//               Core is now a Multimaster I2C controller
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//
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//               Revision 1.4  2002/11/30 22:24:40  rherveille
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//               Cleaned up code
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//
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//               Revision 1.3  2001/11/05 11:59:25  rherveille
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//               Fixed wb_ack_o generation bug.
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//               Fixed bug in the byte_controller statemachine.
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//               Added headers.
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//
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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`include "i2c_master_defines.v"
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module i2c_master_byte_ctrl (
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        clk, rst, nReset, ena, clk_cnt, start, stop, read, write, ack_in, din,
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        cmd_ack, ack_out, dout, i2c_busy, i2c_al, scl_i, scl_o, scl_oen, sda_i, sda_o, sda_oen );
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        //
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        // inputs & outputs
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        //
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        input clk;     // master clock
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        input rst;     // synchronous active high reset
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        input nReset;  // asynchronous active low reset
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        input ena;     // core enable signal
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        input [15:0] clk_cnt; // 4x SCL
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        // control inputs
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        input       start;
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        input       stop;
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        input       read;
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        input       write;
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        input       ack_in;
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        input [7:0] din;
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        // status outputs
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        output       cmd_ack;
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        reg cmd_ack;
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        output       ack_out;
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        reg ack_out;
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        output       i2c_busy;
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        output       i2c_al;
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        output [7:0] dout;
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        // I2C signals
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        input  scl_i;
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        output scl_o;
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        output scl_oen;
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        input  sda_i;
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        output sda_o;
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        output sda_oen;
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        //
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        // Variable declarations
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        //
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        // statemachine
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        parameter [4:0] ST_IDLE  = 5'b0_0000;
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        parameter [4:0] ST_START = 5'b0_0001;
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        parameter [4:0] ST_READ  = 5'b0_0010;
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        parameter [4:0] ST_WRITE = 5'b0_0100;
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        parameter [4:0] ST_ACK   = 5'b0_1000;
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        parameter [4:0] ST_STOP  = 5'b1_0000;
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        // signals for bit_controller
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        reg  [3:0] core_cmd;
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        reg        core_txd;
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        wire       core_ack, core_rxd;
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        // signals for shift register
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        reg [7:0] sr; //8bit shift register
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        reg       shift, ld;
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        // signals for state machine
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        wire       go;
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        reg  [2:0] dcnt;
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        wire       cnt_done;
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        //
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        // Module body
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        //
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        // hookup bit_controller
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        i2c_master_bit_ctrl bit_controller (
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                .clk     ( clk      ),
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                .rst     ( rst      ),
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                .nReset  ( nReset   ),
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                .ena     ( ena      ),
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                .clk_cnt ( clk_cnt  ),
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                .cmd     ( core_cmd ),
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                .cmd_ack ( core_ack ),
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                .busy    ( i2c_busy ),
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                .al      ( i2c_al   ),
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                .din     ( core_txd ),
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                .dout    ( core_rxd ),
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                .scl_i   ( scl_i    ),
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                .scl_o   ( scl_o    ),
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                .scl_oen ( scl_oen  ),
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                .sda_i   ( sda_i    ),
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                .sda_o   ( sda_o    ),
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                .sda_oen ( sda_oen  )
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        );
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        // generate go-signal
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        assign go = (read | write | stop) & ~cmd_ack;
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        // assign dout output to shift-register
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        assign dout = sr;
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        // generate shift register
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        always @(posedge clk or negedge nReset)
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          if (!nReset)
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            sr <= #1 8'h0;
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          else if (rst)
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            sr <= #1 8'h0;
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          else if (ld)
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            sr <= #1 din;
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          else if (shift)
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            sr <= #1 {sr[6:0], core_rxd};
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        // generate counter
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        always @(posedge clk or negedge nReset)
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          if (!nReset)
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            dcnt <= #1 3'h0;
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          else if (rst)
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            dcnt <= #1 3'h0;
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          else if (ld)
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            dcnt <= #1 3'h7;
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          else if (shift)
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            dcnt <= #1 dcnt - 3'h1;
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        assign cnt_done = ~(|dcnt);
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        //
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        // state machine
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        //
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        reg [4:0] c_state; // synopsis enum_state
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        always @(posedge clk or negedge nReset)
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          if (!nReset)
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            begin
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                core_cmd <= #1 `I2C_CMD_NOP;
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                core_txd <= #1 1'b0;
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                shift    <= #1 1'b0;
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                ld       <= #1 1'b0;
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                cmd_ack  <= #1 1'b0;
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                c_state  <= #1 ST_IDLE;
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                ack_out  <= #1 1'b0;
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            end
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          else if (rst | i2c_al)
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           begin
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               core_cmd <= #1 `I2C_CMD_NOP;
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               core_txd <= #1 1'b0;
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               shift    <= #1 1'b0;
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               ld       <= #1 1'b0;
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               cmd_ack  <= #1 1'b0;
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               c_state  <= #1 ST_IDLE;
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               ack_out  <= #1 1'b0;
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           end
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        else
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          begin
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              // initially reset all signals
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              core_txd <= #1 sr[7];
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              shift    <= #1 1'b0;
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              ld       <= #1 1'b0;
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              cmd_ack  <= #1 1'b0;
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              case (c_state) // synopsys full_case parallel_case
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                ST_IDLE:
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                  if (go)
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                    begin
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                        if (start)
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                          begin
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                              c_state  <= #1 ST_START;
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                              core_cmd <= #1 `I2C_CMD_START;
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                          end
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                        else if (read)
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                          begin
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                              c_state  <= #1 ST_READ;
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                              core_cmd <= #1 `I2C_CMD_READ;
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                          end
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                        else if (write)
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                          begin
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                              c_state  <= #1 ST_WRITE;
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                              core_cmd <= #1 `I2C_CMD_WRITE;
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                          end
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                        else // stop
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                          begin
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                              c_state  <= #1 ST_STOP;
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                              core_cmd <= #1 `I2C_CMD_STOP;
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                          end
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                        ld <= #1 1'b1;
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                    end
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                ST_START:
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                  if (core_ack)
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                    begin
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                        if (read)
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                          begin
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                              c_state  <= #1 ST_READ;
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                              core_cmd <= #1 `I2C_CMD_READ;
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                          end
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                        else
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                          begin
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                              c_state  <= #1 ST_WRITE;
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                              core_cmd <= #1 `I2C_CMD_WRITE;
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                          end
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                        ld <= #1 1'b1;
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                    end
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                ST_WRITE:
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                  if (core_ack)
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                    if (cnt_done)
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                      begin
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                          c_state  <= #1 ST_ACK;
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                          core_cmd <= #1 `I2C_CMD_READ;
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                      end
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                    else
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                      begin
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                          c_state  <= #1 ST_WRITE;       // stay in same state
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                          core_cmd <= #1 `I2C_CMD_WRITE; // write next bit
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                          shift    <= #1 1'b1;
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                      end
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                ST_READ:
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                  if (core_ack)
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                    begin
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                        if (cnt_done)
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                          begin
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                              c_state  <= #1 ST_ACK;
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                              core_cmd <= #1 `I2C_CMD_WRITE;
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                          end
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                        else
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                          begin
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                              c_state  <= #1 ST_READ;       // stay in same state
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                              core_cmd <= #1 `I2C_CMD_READ; // read next bit
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                          end
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                        shift    <= #1 1'b1;
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                        core_txd <= #1 ack_in;
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                    end
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                ST_ACK:
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                  if (core_ack)
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                    begin
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                       if (stop)
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                         begin
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                             c_state  <= #1 ST_STOP;
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                             core_cmd <= #1 `I2C_CMD_STOP;
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                         end
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                       else
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                         begin
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                             c_state  <= #1 ST_IDLE;
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                             core_cmd <= #1 `I2C_CMD_NOP;
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                             // generate command acknowledge signal
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                             cmd_ack  <= #1 1'b1;
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                         end
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                         // assign ack_out output to bit_controller_rxd (contains last received bit)
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                         ack_out <= #1 core_rxd;
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327
                         core_txd <= #1 1'b1;
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                     end
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                   else
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                     core_txd <= #1 ack_in;
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                ST_STOP:
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                  if (core_ack)
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                    begin
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                        c_state  <= #1 ST_IDLE;
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                        core_cmd <= #1 `I2C_CMD_NOP;
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                        // generate command acknowledge signal
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                        cmd_ack  <= #1 1'b1;
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                    end
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              endcase
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          end
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endmodule

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