Subversion Repositories i2cslave

# Copyright (C) 1991-2007 Altera Corporation

# Your use of Altera Corporation's design tools, logic functions

# and other software and tools, and its AMPP partner logic

# functions, and any output files from any of the foregoing

# (including device programming or simulation files), and any

# associated documentation or information are expressly subject

# to the terms and conditions of the Altera Program License

# Subscription Agreement, Altera MegaCore Function License

# Agreement, or other applicable license agreement, including,

# without limitation, that your use is for the sole purpose of

# programming logic devices manufactured by Altera and sold by

# Altera or its authorized distributors.  Please refer to the

# applicable agreement for further details.

# The default values for assignments are stored in the file

#               i2cSlaveTopAltera_assignment_defaults.qdf

# If this file doesn't exist, and for assignments not listed, see file

#               assignment_defaults.qdf

# Altera recommends that you do not modify this file. This

# file is updated automatically by the Quartus II software

# and any changes you make may be lost or overwritten.

set_global_assignment -name FAMILY "Cyclone II"

set_global_assignment -name DEVICE EP2C20Q240C8

set_global_assignment -name TOP_LEVEL_ENTITY i2cSlaveTopAltera

set_global_assignment -name ORIGINAL_QUARTUS_VERSION "7.2 SP3"

set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:22:13  DECEMBER 16, 2008"

set_global_assignment -name LAST_QUARTUS_VERSION "7.2 SP3"

set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palace

set_global_assignment -name USER_LIBRARIES ../../rtl/

set_global_assignment -name VERILOG_FILE ../../rtl/timescale.v

set_global_assignment -name VERILOG_FILE ../../rtl/i2cSlave.v

set_global_assignment -name VERILOG_FILE ../../rtl/i2cSlave_define.v

set_global_assignment -name VERILOG_FILE ../../rtl/i2cSlaveTop.v

set_global_assignment -name VERILOG_FILE ../../rtl/registerInterface.v

set_global_assignment -name VERILOG_FILE ../../rtl/serialInterface.v

set_global_assignment -name VERILOG_FILE pll_48MHz.v

set_global_assignment -name VERILOG_FILE i2cSlaveTopAltera.v

set_global_assignment -name NUMBER_OF_PATHS_TO_REPORT 1000

set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF

set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER ON

set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON

set_global_assignment -name SDC_FILE i2cSlaveAlteraTop.sdc

set_global_assignment -name RESERVE_PIN "AS INPUT TRI-STATED"

set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH WEAK PULL-UP"

set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "PASSIVE SERIAL"

set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"

set_location_assignment PIN_30 -to clk

set_location_assignment PIN_46 -to LED

set_location_assignment PIN_41 -to scl

set_location_assignment PIN_42 -to sda

set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top

set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top

set_global_assignment -name PARTITION_COLOR 2147039 -section_id Top

set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"

set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"