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gedra |
----------------------------------------------------------------------
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---- ----
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---- WISHBONE I2S Interface IP Core ----
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---- ----
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---- This file is part of the I2S Interface project ----
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---- http://www.opencores.org/cores/i2s_interface/ ----
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---- ----
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---- Description ----
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---- I2S transmitter/receiver version register. ----
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---- ----
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---- ----
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---- To Do: ----
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---- - ----
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---- ----
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---- Author(s): ----
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---- - Geir Drange, gedra@opencores.org ----
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---- ----
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----------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2004 Authors and OPENCORES.ORG ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.0 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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gedra |
---- PURPOSE. See the GNU General Public License for more details.----
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---- ----
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---- You should have received a copy of the GNU General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.gnu.org/licenses/gpl.txt ----
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---- ----
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----------------------------------------------------------------------
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--
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-- CVS Revision History
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--
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-- $Log: not supported by cvs2svn $
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-- Revision 1.2 2004/08/06 18:55:43 gedra
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-- De-linting.
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--
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-- Revision 1.1 2004/08/03 18:49:03 gedra
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-- Version register.
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--
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--
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--
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gedra |
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity i2s_version is
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generic (DATA_WIDTH : integer;
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ADDR_WIDTH : integer;
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IS_MASTER : integer);
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port (
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ver_rd : in std_logic; -- version register read
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ver_dout : out std_logic_vector(DATA_WIDTH - 1 downto 0)); -- reg. contents
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end i2s_version;
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architecture rtl of i2s_version is
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signal version : std_logic_vector(DATA_WIDTH - 1 downto 0);
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gedra |
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begin
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ver_dout <= version when ver_rd = '1' else (others => '0');
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gedra |
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-- version vector generation
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version(3 downto 0) <= "0001"; -- version 1
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G32 : if DATA_WIDTH = 32 generate
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version(4) <= '1';
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version(31 downto 16) <= (others => '0');
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end generate G32;
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G16 : if DATA_WIDTH = 16 generate
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version(4) <= '0';
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end generate G16;
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version(15 downto 13) <= (others => '0');
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version(12 downto 6) <= std_logic_vector(to_unsigned(ADDR_WIDTH, 7));
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version(5) <= '1' when IS_MASTER = 1 else '0';
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gedra |
end rtl;
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