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[/] [i2s_interface/] [trunk/] [rtl/] [vhdl/] [tx_i2s_pack.vhd] - Blame information for rev 26

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----------------------------------------------------------------------
----                                                              ----
---- WISHBONE I2S Interface IP Core                               ----
----                                                              ----
---- This file is part of the I2S Interface project               ----
---- http://www.opencores.org/cores/i2s_interface/                ----
----                                                              ----
---- Description                                                  ----
---- I2S transmitter component declarations.                      ----
----                                                              ----
---- To Do:                                                       ----
---- -                                                            ----
----                                                              ----
---- Author(s):                                                   ----
---- - Geir Drange, gedra@opencores.org                           ----
----                                                              ----
----------------------------------------------------------------------
----                                                              ----
---- Copyright (C) 2004 Authors and OPENCORES.ORG                 ----
----                                                              ----
---- This source file may be used and distributed without         ----
---- restriction provided that this copyright statement is not    ----
---- removed from the file and that any derivative work contains  ----
---- the original copyright notice and the associated disclaimer. ----
----                                                              ----
---- This source file is free software; you can redistribute it   ----
---- and/or modify it under the terms of the GNU General          ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.0 of the License, or (at your option) any   ----
---- later version.                                               ----
----                                                              ----
---- This source is distributed in the hope that it will be       ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
---- PURPOSE. See the GNU General Public License for more details.----
----                                                              ----
---- You should have received a copy of the GNU General           ----
---- Public License along with this source; if not, download it   ----
---- from http://www.gnu.org/licenses/gpl.txt                     ----
----                                                              ----
----------------------------------------------------------------------
--
-- CVS Revision History
--
-- $Log: not supported by cvs2svn $
-- Revision 1.2  2004/08/06 18:55:43  gedra
-- De-linting.
--
-- Revision 1.1  2004/08/04 14:29:10  gedra
-- Transmitter component declarations.
--
--
--
 
library ieee;
use ieee.std_logic_1164.all;
 
package tx_i2s_pack is
 
-- components used in the transmitter
 
   component gen_control_reg
      generic (DATA_WIDTH      : integer;
               -- note that this vector is (0 to xx), reverse order
               ACTIVE_BIT_MASK : std_logic_vector);
      port (
         clk       : in  std_logic;     -- clock  
         rst       : in  std_logic;     -- reset
         ctrl_wr   : in  std_logic;     -- control register write       
         ctrl_rd   : in  std_logic;     -- control register read
         ctrl_din  : in  std_logic_vector(DATA_WIDTH - 1 downto 0);
         ctrl_dout : out std_logic_vector(DATA_WIDTH - 1 downto 0);
         ctrl_bits : out std_logic_vector(DATA_WIDTH - 1 downto 0));
   end component;
 
   component gen_event_reg
      generic (DATA_WIDTH : integer);
      port (
         clk      : in  std_logic;      -- clock  
         rst      : in  std_logic;      -- reset
         evt_wr   : in  std_logic;      -- event register write  
         evt_rd   : in  std_logic;      -- event register read
         evt_din  : in  std_logic_vector(DATA_WIDTH - 1 downto 0);  -- write data
         event    : in  std_logic_vector(DATA_WIDTH - 1 downto 0);  -- event vector
         evt_mask : in  std_logic_vector(DATA_WIDTH - 1 downto 0);  -- irq mask
         evt_en   : in  std_logic;      -- irq enable
         evt_dout : out std_logic_vector(DATA_WIDTH - 1 downto 0);  -- read data
         evt_irq  : out std_logic);     -- interrupt  request
   end component;
 
   component dpram
      generic (DATA_WIDTH : positive;
               RAM_WIDTH  : positive);
      port (
         clk     : in  std_logic;
         rst     : in  std_logic;       -- reset is optional, not used here
         din     : in  std_logic_vector(DATA_WIDTH - 1 downto 0);
         wr_en   : in  std_logic;
         rd_en   : in  std_logic;
         wr_addr : in  std_logic_vector(RAM_WIDTH - 1 downto 0);
         rd_addr : in  std_logic_vector(RAM_WIDTH - 1 downto 0);
         dout    : out std_logic_vector(DATA_WIDTH - 1 downto 0));
   end component;
 
   component i2s_version
      generic (DATA_WIDTH : integer;
               ADDR_WIDTH : integer;
               IS_MASTER  : integer);
      port (
         ver_rd   : in  std_logic;      -- version register read
         ver_dout : out std_logic_vector(DATA_WIDTH - 1 downto 0));
   end component;
 
   component tx_i2s_wbd
      generic (DATA_WIDTH : integer;
               ADDR_WIDTH : integer);
      port (
         wb_clk_i   : in  std_logic;    -- wishbone clock
         wb_rst_i   : in  std_logic;    -- reset signal
         wb_sel_i   : in  std_logic;    -- select input
         wb_stb_i   : in  std_logic;    -- strobe input
         wb_we_i    : in  std_logic;    -- write enable
         wb_cyc_i   : in  std_logic;    -- cycle input
         wb_bte_i   : in  std_logic_vector(1 downto 0);  -- burts type extension
         wb_cti_i   : in  std_logic_vector(2 downto 0);  -- cycle type identifier
         wb_adr_i   : in  std_logic_vector(ADDR_WIDTH - 1 downto 0);  -- address
         data_out   : in  std_logic_vector(DATA_WIDTH - 1 downto 0);  -- internal bus
         wb_ack_o   : out std_logic;    -- acknowledge
         wb_dat_o   : out std_logic_vector(DATA_WIDTH - 1 downto 0);  -- data out
         version_rd : out std_logic;    -- Version register read 
         config_rd  : out std_logic;    -- Config register read
         config_wr  : out std_logic;    -- Config register write
         intmask_rd : out std_logic;    -- Interrupt mask register read
         intmask_wr : out std_logic;    -- Interrupt mask register write
         intstat_rd : out std_logic;    -- Interrupt status register read
         intstat_wr : out std_logic;    -- Interrupt status register read
         mem_wr     : out std_logic);   -- Sample memory write
   end component;
 
   component i2s_codec
      generic (DATA_WIDTH  : integer;
               ADDR_WIDTH  : integer;
               IS_MASTER   : integer range 0 to 1;
               IS_RECEIVER : integer range 0 to 1);
      port (
         wb_clk_i     : in  std_logic;  -- wishbone clock
         conf_res     : in  std_logic_vector(5 downto 0);  -- sample resolution
         conf_ratio   : in  std_logic_vector(7 downto 0);  -- clock divider ratio
         conf_swap    : in  std_logic;  -- left/right sample order
         conf_en      : in  std_logic;  -- transmitter/recevier enable
         i2s_sd_i     : in  std_logic;  -- I2S serial data input
         i2s_sck_i    : in  std_logic;  -- I2S clock input
         i2s_ws_i     : in  std_logic;  -- I2S word select input
         sample_dat_i : in  std_logic_vector(DATA_WIDTH - 1 downto 0);  -- audio data
         sample_dat_o : out std_logic_vector(DATA_WIDTH - 1 downto 0);  -- audio data
         mem_rdwr     : out std_logic;  -- sample buffer read/write
         sample_addr  : out std_logic_vector(ADDR_WIDTH - 2 downto 0);  -- address
         evt_hsbf     : out std_logic;  -- higher sample buf empty event
         evt_lsbf     : out std_logic;  -- lower sample buf empty event
         i2s_sd_o     : out std_logic;  -- I2S serial data output
         i2s_sck_o    : out std_logic;  -- I2S clock output
         i2s_ws_o     : out std_logic);  -- I2S word select output
   end component;
 
end tx_i2s_pack;

Line No.	Rev	Author	Line
1	11	gedra	`----------------------------------------------------------------------`
2			`---- ----`
3			`---- WISHBONE I2S Interface IP Core ----`
4			`---- ----`
5			`---- This file is part of the I2S Interface project ----`
6			`---- http://www.opencores.org/cores/i2s_interface/ ----`
7			`---- ----`
8			`---- Description ----`
9			`---- I2S transmitter component declarations. ----`
10			`---- ----`
11			`---- To Do: ----`
12			`---- - ----`
13			`---- ----`
14			`---- Author(s): ----`
15			`---- - Geir Drange, gedra@opencores.org ----`
16			`---- ----`
17			`----------------------------------------------------------------------`
18			`---- ----`
19			`---- Copyright (C) 2004 Authors and OPENCORES.ORG ----`
20			`---- ----`
21			`---- This source file may be used and distributed without ----`
22			`---- restriction provided that this copyright statement is not ----`
23			`---- removed from the file and that any derivative work contains ----`
24			`---- the original copyright notice and the associated disclaimer. ----`
25			`---- ----`
26			`---- This source file is free software; you can redistribute it ----`
27			`---- and/or modify it under the terms of the GNU General ----`
28			`---- Public License as published by the Free Software Foundation; ----`
29			`---- either version 2.0 of the License, or (at your option) any ----`
30			`---- later version. ----`
31			`---- ----`
32			`---- This source is distributed in the hope that it will be ----`
33			`---- useful, but WITHOUT ANY WARRANTY; without even the implied ----`
34			`---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----`
35	18	gedra	`---- PURPOSE. See the GNU General Public License for more details.----`
36	11	gedra	`---- ----`
37			`---- You should have received a copy of the GNU General ----`
38			`---- Public License along with this source; if not, download it ----`
39			`---- from http://www.gnu.org/licenses/gpl.txt ----`
40			`---- ----`
41			`----------------------------------------------------------------------`
42			`--`
43			`-- CVS Revision History`
44			`--`
45			`-- $Log: not supported by cvs2svn $`
46	24	gedra	`-- Revision 1.2 2004/08/06 18:55:43 gedra`
47			`-- De-linting.`
48			`--`
49	18	gedra	`-- Revision 1.1 2004/08/04 14:29:10 gedra`
50			`-- Transmitter component declarations.`
51	11	gedra	`--`
52			`--`
53	18	gedra	`--`
54	24	gedra
55	11	gedra	`library ieee;`
56	24	gedra	`use ieee.std_logic_1164.all;`
57	11	gedra
58			`package tx_i2s_pack is`
59	24	gedra
60	11	gedra	`-- components used in the transmitter`
61	24	gedra
62			`component gen_control_reg`
63			`generic (DATA_WIDTH : integer;`
64			`-- note that this vector is (0 to xx), reverse order`
65			`ACTIVE_BIT_MASK : std_logic_vector);`
66			`port (`
67			`clk : in std_logic; -- clock`
68			`rst : in std_logic; -- reset`
69			`ctrl_wr : in std_logic; -- control register write`
70			`ctrl_rd : in std_logic; -- control register read`
71			`ctrl_din : in std_logic_vector(DATA_WIDTH - 1 downto 0);`
72			`ctrl_dout : out std_logic_vector(DATA_WIDTH - 1 downto 0);`
73			`ctrl_bits : out std_logic_vector(DATA_WIDTH - 1 downto 0));`
74			`end component;`
75	11	gedra
76	24	gedra	`component gen_event_reg`
77			`generic (DATA_WIDTH : integer);`
78			`port (`
79			`clk : in std_logic; -- clock`
80			`rst : in std_logic; -- reset`
81			`evt_wr : in std_logic; -- event register write`
82			`evt_rd : in std_logic; -- event register read`
83			`evt_din : in std_logic_vector(DATA_WIDTH - 1 downto 0); -- write data`
84			`event : in std_logic_vector(DATA_WIDTH - 1 downto 0); -- event vector`
85			`evt_mask : in std_logic_vector(DATA_WIDTH - 1 downto 0); -- irq mask`
86			`evt_en : in std_logic; -- irq enable`
87			`evt_dout : out std_logic_vector(DATA_WIDTH - 1 downto 0); -- read data`
88			`evt_irq : out std_logic); -- interrupt request`
89			`end component;`
90	11	gedra
91	24	gedra	`component dpram`
92			`generic (DATA_WIDTH : positive;`
93			`RAM_WIDTH : positive);`
94			`port (`
95			`clk : in std_logic;`
96			`rst : in std_logic; -- reset is optional, not used here`
97			`din : in std_logic_vector(DATA_WIDTH - 1 downto 0);`
98			`wr_en : in std_logic;`
99			`rd_en : in std_logic;`
100			`wr_addr : in std_logic_vector(RAM_WIDTH - 1 downto 0);`
101			`rd_addr : in std_logic_vector(RAM_WIDTH - 1 downto 0);`
102			`dout : out std_logic_vector(DATA_WIDTH - 1 downto 0));`
103			`end component;`
104	11	gedra
105	24	gedra	`component i2s_version`
106			`generic (DATA_WIDTH : integer;`
107			`ADDR_WIDTH : integer;`
108			`IS_MASTER : integer);`
109			`port (`
110			`ver_rd : in std_logic; -- version register read`
111			`ver_dout : out std_logic_vector(DATA_WIDTH - 1 downto 0));`
112			`end component;`
113	11	gedra
114	24	gedra	`component tx_i2s_wbd`
115			`generic (DATA_WIDTH : integer;`
116			`ADDR_WIDTH : integer);`
117			`port (`
118			`wb_clk_i : in std_logic; -- wishbone clock`
119			`wb_rst_i : in std_logic; -- reset signal`
120			`wb_sel_i : in std_logic; -- select input`
121			`wb_stb_i : in std_logic; -- strobe input`
122			`wb_we_i : in std_logic; -- write enable`
123			`wb_cyc_i : in std_logic; -- cycle input`
124			`wb_bte_i : in std_logic_vector(1 downto 0); -- burts type extension`
125			`wb_cti_i : in std_logic_vector(2 downto 0); -- cycle type identifier`
126			`wb_adr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0); -- address`
127			`data_out : in std_logic_vector(DATA_WIDTH - 1 downto 0); -- internal bus`
128			`wb_ack_o : out std_logic; -- acknowledge`
129			`wb_dat_o : out std_logic_vector(DATA_WIDTH - 1 downto 0); -- data out`
130			`version_rd : out std_logic; -- Version register read`
131			`config_rd : out std_logic; -- Config register read`
132			`config_wr : out std_logic; -- Config register write`
133			`intmask_rd : out std_logic; -- Interrupt mask register read`
134			`intmask_wr : out std_logic; -- Interrupt mask register write`
135			`intstat_rd : out std_logic; -- Interrupt status register read`
136			`intstat_wr : out std_logic; -- Interrupt status register read`
137			`mem_wr : out std_logic); -- Sample memory write`
138			`end component;`
139	11	gedra
140	24	gedra	`component i2s_codec`
141			`generic (DATA_WIDTH : integer;`
142			`ADDR_WIDTH : integer;`
143			`IS_MASTER : integer range 0 to 1;`
144			`IS_RECEIVER : integer range 0 to 1);`
145			`port (`
146			`wb_clk_i : in std_logic; -- wishbone clock`
147			`conf_res : in std_logic_vector(5 downto 0); -- sample resolution`
148			`conf_ratio : in std_logic_vector(7 downto 0); -- clock divider ratio`
149			`conf_swap : in std_logic; -- left/right sample order`
150			`conf_en : in std_logic; -- transmitter/recevier enable`
151			`i2s_sd_i : in std_logic; -- I2S serial data input`
152			`i2s_sck_i : in std_logic; -- I2S clock input`
153			`i2s_ws_i : in std_logic; -- I2S word select input`
154			`sample_dat_i : in std_logic_vector(DATA_WIDTH - 1 downto 0); -- audio data`
155			`sample_dat_o : out std_logic_vector(DATA_WIDTH - 1 downto 0); -- audio data`
156			`mem_rdwr : out std_logic; -- sample buffer read/write`
157			`sample_addr : out std_logic_vector(ADDR_WIDTH - 2 downto 0); -- address`
158			`evt_hsbf : out std_logic; -- higher sample buf empty event`
159			`evt_lsbf : out std_logic; -- lower sample buf empty event`
160			`i2s_sd_o : out std_logic; -- I2S serial data output`
161			`i2s_sck_o : out std_logic; -- I2S clock output`
162			`i2s_ws_o : out std_logic); -- I2S word select output`
163			`end component;`
164	11	gedra
165			`end tx_i2s_pack;`

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[/] [i2s_interface/] [trunk/] [rtl/] [vhdl/] [tx_i2s_pack.vhd] - Blame information for rev 26