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[/] [i2s_interface/] [trunk/] [rtl/] [vhdl/] [tx_i2s_wbd.vhd] - Blame information for rev 22

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1 9 gedra 
----------------------------------------------------------------------
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----                                                              ----
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---- WISHBONE I2S Interface IP Core                               ----
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----                                                              ----
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---- This file is part of the I2S Interface project               ----
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---- http://www.opencores.org/cores/i2s_interface/                ----
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----                                                              ----
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---- Description                                                  ----
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---- I2S transmitter Wishbone bus cycle decoder.                  ----
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----                                                              ----
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----                                                              ----
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---- To Do:                                                       ----
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---- -                                                            ----
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----                                                              ----
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---- Author(s):                                                   ----
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---- - Geir Drange, gedra@opencores.org                           ----
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----                                                              ----
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----------------------------------------------------------------------
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----                                                              ----
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---- Copyright (C) 2004 Authors and OPENCORES.ORG                 ----
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----                                                              ----
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---- This source file may be used and distributed without         ----
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---- restriction provided that this copyright statement is not    ----
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---- removed from the file and that any derivative work contains  ----
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---- the original copyright notice and the associated disclaimer. ----
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----                                                              ----
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---- This source file is free software; you can redistribute it   ----
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---- and/or modify it under the terms of the GNU General          ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.0 of the License, or (at your option) any   ----
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---- later version.                                               ----
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----                                                              ----
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---- This source is distributed in the hope that it will be       ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
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---- PURPOSE. See the GNU General Public License for more details.----
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----                                                              ----
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---- You should have received a copy of the GNU General           ----
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---- Public License along with this source; if not, download it   ----
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---- from http://www.gnu.org/licenses/gpl.txt                     ----
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----                                                              ----
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----------------------------------------------------------------------
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--
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-- CVS Revision History
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--
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-- $Log: not supported by cvs2svn $
47 22 gedra 
-- Revision 1.2  2004/08/06 18:55:43  gedra
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-- De-linting.
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--
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-- Revision 1.1  2004/08/03 18:50:51  gedra
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-- Transmitter Wishbone cycle decoder.
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--
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--
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity tx_i2s_wbd is
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  generic (DATA_WIDTH: integer;
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           ADDR_WIDTH: integer);
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  port (
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    wb_clk_i: in std_logic;             -- wishbone clock
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    wb_rst_i: in std_logic;             -- reset signal
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    wb_sel_i: in std_logic;             -- select input
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    wb_stb_i: in std_logic;             -- strobe input
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    wb_we_i: in std_logic;              -- write enable
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    wb_cyc_i: in std_logic;             -- cycle input
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    wb_bte_i: in std_logic_vector(1 downto 0);  -- burts type extension
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    wb_cti_i: in std_logic_vector(2 downto 0);  -- cycle type identifier
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    wb_adr_i: in std_logic_vector(ADDR_WIDTH - 1 downto 0);  -- address
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    data_out: in std_logic_vector(DATA_WIDTH - 1 downto 0); -- internal bus
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    wb_ack_o: out std_logic;            -- acknowledge
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    wb_dat_o: out std_logic_vector(DATA_WIDTH - 1 downto 0);  -- data out
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    version_rd: out std_logic;          -- Version register read
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    config_rd: out std_logic;           -- Config register read
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    config_wr: out std_logic;           -- Config register write
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    intmask_rd: out std_logic;          -- Interrupt mask register read
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    intmask_wr: out std_logic;          -- Interrupt mask register write
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    intstat_rd: out std_logic;          -- Interrupt status register read
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    intstat_wr: out std_logic;          -- Interrupt status register read
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    mem_wr: out std_logic);             -- Sample memory write
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end tx_i2s_wbd;
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architecture rtl of tx_i2s_wbd is
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  constant REG_TXVERSION : std_logic_vector(3 downto 0) := "0000";
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  constant REG_TXCONFIG  : std_logic_vector(3 downto 0) := "0001";
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  constant REG_TXINTMASK : std_logic_vector(3 downto 0) := "0010";
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  constant REG_TXINTSTAT : std_logic_vector(3 downto 0) := "0011";
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  signal iack, iwr, ird : std_logic;
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  signal acnt: integer range 0 to 2**(ADDR_WIDTH - 1) - 1;
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  signal rdout : std_logic_vector(DATA_WIDTH - 1 downto 0);
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begin
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  wb_ack_o <= iack;
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-- acknowledge generation
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  ACK: process (wb_clk_i, wb_rst_i)
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  begin
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    if wb_rst_i = '1' then
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      iack <= '0';
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    elsif rising_edge(wb_clk_i) then
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      if wb_cyc_i = '1' and wb_sel_i = '1' and wb_stb_i = '1' then
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        case wb_cti_i is
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          when "010" => -- incrementing burst
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            case wb_bte_i is -- burst extension
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              when "00" => -- linear burst
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                iack <= '1';
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              when others => -- all other treated assert classic cycle
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                iack <= not iack;
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            end case;
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          when "111" => -- end of burst
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            iack <= not iack;
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          when others => -- all other treated assert classic cycle
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            iack <= not iack;
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        end case;
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      else
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        iack <= '0';
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      end if;
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    end if;
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  end process ACK;
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-- write generation
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  WR: process (wb_clk_i, wb_rst_i)
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  begin
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    if wb_rst_i = '1' then
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      iwr <= '0';
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    elsif rising_edge(wb_clk_i) then
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      if wb_cyc_i = '1' and wb_sel_i = '1' and wb_stb_i = '1' and
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        wb_we_i = '1' then
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        case wb_cti_i is
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          when "010" => -- incrementing burst
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            case wb_bte_i is -- burst extension
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              when "00" => -- linear burst
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                iwr <= '1';
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              when others => -- all other treated as classic cycle
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                iwr <= not iwr;
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            end case;
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          when "111" => -- end of burst
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            iwr <= not iwr;
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          when others => -- all other treated as classic cycle
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            iwr <= not iwr;
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        end case;
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      else
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        iwr <= '0';
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      end if;
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    end if;
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  end process WR;
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-- read generation
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  ird <= '1' when wb_cyc_i = '1' and wb_sel_i = '1' and wb_stb_i = '1' and
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         wb_we_i = '0' else '0';
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  wb_dat_o <= data_out when wb_adr_i(ADDR_WIDTH - 1) = '1' else rdout;
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  DREG: process (wb_clk_i)              -- clock data from registers
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  begin
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    if rising_edge(wb_clk_i) then
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      rdout <= data_out;
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    end if;
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  end process DREG;
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-- read and write strobe generation
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  version_rd <= '1' when wb_adr_i(3 downto 0) = REG_TXVERSION and ird = '1'
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                and wb_adr_i(ADDR_WIDTH - 1) = '0' else '0';
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  config_rd <= '1' when wb_adr_i(3 downto 0) = REG_TXCONFIG and ird = '1'
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               and wb_adr_i(ADDR_WIDTH - 1) = '0' else '0';
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  config_wr <= '1' when wb_adr_i(3 downto 0) = REG_TXCONFIG and iwr = '1'
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               and wb_adr_i(ADDR_WIDTH - 1) = '0' else '0';
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  intmask_rd <= '1' when wb_adr_i(3 downto 0) = REG_TXINTMASK and ird = '1'
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                and wb_adr_i(ADDR_WIDTH - 1) = '0' else '0';
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  intmask_wr <= '1' when wb_adr_i(3 downto 0) = REG_TXINTMASK and iwr = '1'
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                and wb_adr_i(ADDR_WIDTH - 1) = '0' else '0';
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  intstat_rd <= '1' when wb_adr_i(3 downto 0) = REG_TXINTSTAT and ird = '1'
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                and wb_adr_i(ADDR_WIDTH - 1) = '0' else '0';
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  intstat_wr <= '1' when wb_adr_i(3 downto 0) = REG_TXINTSTAT and iwr = '1'
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                else '0';
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  mem_wr <= '1' when wb_adr_i(ADDR_WIDTH - 1) = '1' and iwr = '1' else '0';
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end rtl;

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