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[/ ] [i2sparalell/ ] [trunk/ ] [I2SParalell.ucf ] - Blame information for rev 3
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2 franksdeve
# Clock
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NET "Xtal" PERIOD = 40; # 40ns = 25MHz
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# A/D Fifo Interface
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# FIFO CTRL
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# ADC/DAC
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# EOF
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#PACE: Start of Constraints generated by PACE
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#PACE: Start of PACE I/O Pin Assignments
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NET "AdcData" LOC = "P2" | PULLUP ; #PullUp for I2S on CS5340; PullDn is LJ mode, which causes 1-bit timing error (volume/2)| #PullUp for I2S on CS5340; PullDn is LJ mode, which causes 1-bit timing error (volume/2)
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NET "ADCSampleBus<0>" LOC = "P18" ; # AvrA7
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NET "ADCSampleBus<1>" LOC = "P16" ; # AvrA6
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NET "ADCSampleBus<2>" LOC = "P14" ; # AvrA5
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NET "ADCSampleBus<3>" LOC = "P13" ; # AvrA4
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NET "ADCSampleBus<4>" LOC = "P12" ; # AvrA3
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NET "ADCSampleBus<6>" LOC = "P7" ; # AvrA1
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NET "DacData" LOC = "P5" ;
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NET "DACSampleBus<0>" LOC = "P19" ; # AvrC7
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NET "DACSampleBus<1>" LOC = "P20" ; # AvrC6
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NET "DACSampleBus<2>" LOC = "P21" ; # AvrC5
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NET "DACSampleBus<3>" LOC = "P22" ; # AvrC4
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NET "DACSampleBus<4>" LOC = "P23" ; # AvrC3
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NET "DACSampleBus<6>" LOC = "P28" ; # AvrC1
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NET "LDataStrobe" LOC = "P40" ; # alias e5
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NET "LRClk" LOC = "P42" ;
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NET "MClk" LOC = "P3" ;
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NET "nDebugLoopBack" LOC = "P30" | PULLUP ;
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NET "RDataStrobe" LOC = "P41" ; # alias e4
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NET "SClk" LOC = "P4" ;
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NET "Xtal" LOC = "P43" ; # Clock input - GCLK0
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#PACE: Start of PACE Area Constraints
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#PACE: Start of PACE Prohibit Constraints
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#PACE: End of Constraints generated by PACE
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