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[/] [i650/] [trunk/] [rtl/] [add_in_a.v] - Blame information for rev 21

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1 21 eightycc
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// IBM 650 Reconstruction in Verilog (i650)
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// 
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// This file is part of the IBM 650 Reconstruction in Verilog (i650) project
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// http:////www.opencores.org/project,i650
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//
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// Description: Adder input A.
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// 
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// Additional Comments: See US 2959351, Fig. 66.
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//
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// Copyright (c) 2015 Robert Abeles
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//
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// This source file is free software; you can redistribute it
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// and/or modify it under the terms of the GNU Lesser General
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// Public License as published by the Free Software Foundation;
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// either version 2.1 of the License, or (at your option) any
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// later version.
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//
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// This source is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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// PURPOSE.  See the GNU Lesser General Public License for more
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// details.
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//
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// You should have received a copy of the GNU Lesser General
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// Public License along with this source; if not, download it
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// from http://www.opencores.org/lgpl.shtml
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//////////////////////////////////////////////////////////////////////////////////
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`include "defines.v"
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module add_in_a (
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   input [0:6] acc_early_out, acc_ontime_out, prog_step_early_out,
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               select_storage_out, addr_u,
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   input acc_true_add_gate, acc_compl_add_gate,
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         left_shift_gate, prog_step_add_gate, shift_num_gate,
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         select_stor_add_gate,
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   output [0:6] adder_entry_a
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   );
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   wire [0:6] acc_early_compl;   // 9's complement
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   biq_9s_comp bc1 (acc_early_out, acc_early_compl);
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   wire [0:6] addr_u_compl;
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   biq_9s_comp bc2 (addr_u, addr_u_compl);
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   assign adder_entry_a = acc_true_add_gate?    acc_early_out
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                        : acc_compl_add_gate?   acc_early_compl
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                        : left_shift_gate?      acc_ontime_out
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                        : prog_step_add_gate?   prog_step_early_out
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                        : shift_num_gate?       addr_u_compl
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                        : select_stor_add_gate? select_storage_out
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                        :                       `biq_blank;
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endmodule

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