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eightycc |
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// IBM 650 Reconstruction in Verilog (i650)
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//
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// This file is part of the IBM 650 Reconstruction in Verilog (i650) project
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// http:////www.opencores.org/project,i650
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//
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// Description: Adder input B.
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//
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// Additional Comments: See US 2959351, Fig. 67.
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//
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// Copyright (c) 2015 Robert Abeles
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//
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// This source file is free software; you can redistribute it
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// and/or modify it under the terms of the GNU Lesser General
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// Public License as published by the Free Software Foundation;
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// either version 2.1 of the License, or (at your option) any
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// later version.
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//
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// This source is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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// PURPOSE. See the GNU Lesser General Public License for more
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// details.
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//
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// You should have received a copy of the GNU Lesser General
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// Public License along with this source; if not, download it
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// from http://www.opencores.org/lgpl.shtml
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//////////////////////////////////////////////////////////////////////////////////
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`include "defines.v"
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module add_in_b (
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input [0:6] dist_early_out, dist_ontime_out,
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input [0:9] special_int_entry,
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input ontime_dist_add_gate_tlu, dist_compl_add_gate, upper_lower_check,
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dist_blank_gate, early_dist_zero_entry, //early_dist_zero_ctrl,
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dist_true_add_gate,
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output [0:6] adder_entry_b
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);
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wire [0:6] special_int_biq = special_int_entry[0]? `biq_0
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: special_int_entry[1]? `biq_1
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: special_int_entry[2]? `biq_2
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: special_int_entry[3]? `biq_3
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: special_int_entry[4]? `biq_4
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: special_int_entry[5]? `biq_5
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: special_int_entry[6]? `biq_6
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: special_int_entry[7]? `biq_7
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: special_int_entry[8]? `biq_8
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: special_int_entry[9]? `biq_9
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: `biq_blank;
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wire [0:6] dist_early_compl;
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biq_9s_comp bc1 (dist_early_out, dist_early_compl);
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wire dist_true_add = dist_true_add_gate & upper_lower_check & dist_blank_gate;
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wire dist_compl_add = dist_compl_add_gate & upper_lower_check & dist_blank_gate;
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assign adder_entry_b = early_dist_zero_entry? `biq_0
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: dist_true_add? dist_early_out
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: dist_compl_add? dist_early_compl
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: ontime_dist_add_gate_tlu? dist_ontime_out
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: special_int_biq;
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endmodule
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