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[/] [i650/] [trunk/] [rtl/] [addr_reg.v] - Blame information for rev 27

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1 21 eightycc 
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// IBM 650 Reconstruction in Verilog (i650)
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//
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// This file is part of the IBM 650 Reconstruction in Verilog (i650) project
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// http:////www.opencores.org/project,i650
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//
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// Description: Address register.
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//
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// Additional Comments: See US 2959351, Fig. 71.
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//
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// Copyright (c) 2015 Robert Abeles
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//
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// This source file is free software; you can redistribute it
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// and/or modify it under the terms of the GNU Lesser General
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// Public License as published by the Free Software Foundation;
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// either version 2.1 of the License, or (at your option) any
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// later version.
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//
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// This source is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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// PURPOSE.  See the GNU Lesser General Public License for more
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// details.
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//
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// You should have received a copy of the GNU Lesser General
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// Public License along with this source; if not, download it
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// from http://www.opencores.org/lgpl.shtml
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//////////////////////////////////////////////////////////////////////////////////
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`include "defines.v"
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module addr_reg (
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    input rst,
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    input ap, bp,
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    input dx, d1, d2, d3, d4, d5, d6, d7, d8, d9,
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    input w0, w1, w2, w3, w4, w5, w6, w7, w8, w9,
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    input s0, s1, s2, s3, s4,
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    input error_reset,
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    input restart_a,
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    input set_8000, reset_8000,
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    input tlu_band_change,
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    input double_write,
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    input no_write,
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    input bs_to_gs,
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    input rigs,
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    input [0:6] ps_reg_in, console_in,
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    input ri_addr_reg,
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    input console_to_addr_reg,
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    output reg[0:6] addr_th, addr_h, addr_t, addr_u,
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    output reg dynamic_addr_hit,
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    output reg addr_no_800x, addr_8000, addr_8001, addr_8002,
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               addr_8003, addr_8002_8003,
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    output reg invalid_addr
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    );
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   wire reset_to_0000 =  (d1 & tlu_band_change)
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                       | restart_a
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                       | reset_8000;
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   always @(posedge bp)
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      if (rst) begin
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         addr_th <= `biq_0;
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         addr_h  <= `biq_0;
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         addr_t  <= `biq_0;
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         addr_u  <= `biq_0;
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      end else if (set_8000) begin
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         addr_th <= `biq_8;
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         addr_h  <= `biq_0;
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         addr_t  <= `biq_0;
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         addr_u  <= `biq_0;
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      end else if (reset_to_0000) begin
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         addr_th <= `biq_0;
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         addr_h  <= `biq_0;
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         addr_t  <= `biq_0;
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         addr_u  <= `biq_0;
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      end else if (ri_addr_reg) begin
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         if (d4 | d8) addr_th <= ps_reg_in;
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         else if (d3 | d7) addr_h <= ps_reg_in;
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         else if (d2 | d6) addr_t <= ps_reg_in;
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         else if (d1 | d5) addr_u <= ps_reg_in;
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      end else if (console_to_addr_reg) begin
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         if (d4) addr_th <= console_in;
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         else if (d3) addr_h <= console_in;
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         else if (d2) addr_t <= console_in;
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         else if (d1) addr_u <= console_in;
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      end;
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   // Find whether next word coincides with address register (dynamic portion of address)
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   // Sample at d9:ap
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   assign q4un_p = addr_u[`biq_q4] & (w3 | w8);
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   assign q3un_p = addr_u[`biq_q3] & (w2 | w7);
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   assign q2un_p = addr_u[`biq_q2] & (w1 | w6);
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   assign q1un_p = addr_u[`biq_q1] & (w0 | w5);
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   assign q0un_p = addr_u[`biq_q0] & (w4 | w9);
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   assign b0un_p = addr_u[`biq_b0] & (w0 | w1 | w2 | w3 | w9);
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   assign b5un_p = addr_u[`biq_b5] & (w4 | w5 | w6 | w7 | w8);
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   assign q4t_p = addr_t[`biq_q4] & w9 & s3 | addr_t[`biq_q4] & ~w9 & s4;
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   assign q3t_p = addr_t[`biq_q3] & w9 & s2 | addr_t[`biq_q3] & ~w9 & s3;
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   assign q2t_p = addr_t[`biq_q2] & w9 & s1 | addr_t[`biq_q2] & ~w9 & s2;
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   assign q1t_p = addr_t[`biq_q1] & w9 & s0 | addr_t[`biq_q1] & ~w9 & s1;
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   assign q0t_p = addr_t[`biq_q0] & w9 & s4 | addr_t[`biq_q0] & ~w9 & s0;
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   assign dynamic_addr_hit_p = (q4un_p | q3un_p | q2un_p | q1un_p | q0un_p)
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                             & (b0un_p | b5un_p) & (q4t_p | q3t_p | q2t_p | q1t_p | q0t_p);
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   // Test address register validity
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   //    Test address == 0xxx or == 1xxx or == 800[0..3]
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   assign inv1_p = (addr_th[2] | addr_th[4]) | (addr_th[3] & addr_th[1])
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                 | (addr_th[6] & addr_th[0]) | (addr_th[5] & addr_th[0]);  // 0xxx or 1xxx or 8xxx
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   assign inv2_p = (addr_th[3] & addr_th[0]) & ~(addr_h[1] & addr_h[6]);   // 80xx
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   assign inv3_p = (addr_th[3] & addr_th[0]) & ~(addr_t[1] & addr_t[6]);   // 8x0x
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   assign inv4_p = (addr_th[3] & addr_th[0]) & (addr_u[0] | addr_u[2]);    // 8xx[0..3]
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   assign invalid_addr_p = inv1_p | inv2_p | inv3_p | inv4_p;
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   // Decode 8xxx addresses
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   assign addr_8xxx_p = (addr_th[`biq_b5] & addr_th[`biq_q3]);
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   assign addr_8xx0_p = addr_8xxx_p & addr_u[`biq_q0];
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   assign addr_8xx1_p = addr_8xxx_p & addr_u[`biq_q1];
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   assign addr_8xx2_p = addr_8xxx_p & addr_u[`biq_q2];
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   assign addr_8xx3_p = addr_8xxx_p & addr_u[`biq_q3];
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   // Memory access error
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   assign mem_error_p = double_write | ((bs_to_gs | rigs) & ~dx & no_write);
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   always @(posedge ap)
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      if (rst) begin
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         invalid_addr <= 0;
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      end else if (error_reset | ri_addr_reg | console_to_addr_reg) begin
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         invalid_addr <= 0;
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      end else if (mem_error_p | invalid_addr_p) begin
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         invalid_addr <= 1;
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      end;
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   always @(posedge ap)
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      if (rst) begin
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         dynamic_addr_hit <= 0;
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      end else if (d9) begin
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         dynamic_addr_hit <= dynamic_addr_hit_p;
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      end else if (dx) begin
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         dynamic_addr_hit <= 0;
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      end;
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   always @(posedge bp)
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      if (rst) begin
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         addr_no_800x <= 1;
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         addr_8000 <= 0;
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         addr_8001 <= 0;
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         addr_8002 <= 0;
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         addr_8003 <= 0;
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         addr_8002_8003 <= 0;
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      end else begin
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         addr_no_800x <= ~addr_8xxx_p & ~invalid_addr_p;
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         addr_8000 <= addr_8xx0_p & ~invalid_addr_p;
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         addr_8001 <= addr_8xx1_p & ~invalid_addr_p;
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         addr_8002 <= addr_8xx2_p & ~invalid_addr_p;
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         addr_8003 <= addr_8xx3_p & ~invalid_addr_p;
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         addr_8002_8003 <= (addr_8xx2_p | addr_8xx3_p) & ~invalid_addr_p;
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      end;
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endmodule

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