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eightycc |
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// IBM 650 Reconstruction in Verilog (i650)
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//
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// This file is part of the IBM 650 Reconstruction in Verilog (i650) project
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// http:////www.opencores.org/project,i650
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//
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// Description: Distributor register.
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//
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// Additional Comments: See US 2959351, Fig. 61.
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//
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// Copyright (c) 2015 Robert Abeles
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//
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// This source file is free software; you can redistribute it
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// and/or modify it under the terms of the GNU Lesser General
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// Public License as published by the Free Software Foundation;
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// either version 2.1 of the License, or (at your option) any
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// later version.
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//
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// This source is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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// PURPOSE. See the GNU Lesser General Public License for more
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// details.
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//
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// You should have received a copy of the GNU Lesser General
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// Public License along with this source; if not, download it
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// from http://www.opencores.org/lgpl.shtml
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//////////////////////////////////////////////////////////////////////////////////
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`include "defines.v"
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module distributor (
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input rst,
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input ap, cp, dp,
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input dx, d0, d10,
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input [0:6] selected_storage,
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input ri_dist, // commutator 81f, dx:bp
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input [0:6] acc_ontime,
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input start_acc_dist_ri, end_acc_dist_ri, acc_dist_ri,
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input man_acc_reset,
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input [0:3] early_idx, ontime_idx,
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output reg[0:6] ontime_out, early_out,
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output dist_back_sig
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);
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reg [0:6] digits [0:15];
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reg ri_dist_from_stor, dist_regen_ctl, ri_from_acc, ri_from_acc_delay;
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//-----------------------------------------------------------------------------
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// A -- Read digits RAM, write early and ontime outs
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//-----------------------------------------------------------------------------
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always @(posedge ap)
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if (rst) begin
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early_out <= `biq_blank;
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ontime_out <= `biq_blank;
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end else begin
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early_out <= (dist_regen_ctl | d10)? `biq_blank : digits[early_idx];
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ontime_out <= dx? `biq_0
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: man_acc_reset? (d0? `biq_plus : `biq_0)
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: early_out;
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end;
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//-----------------------------------------------------------------------------
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// C
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//-----------------------------------------------------------------------------
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always @(posedge cp)
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if (rst) begin
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ri_dist_from_stor <= 0;
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dist_regen_ctl <= 0;
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ri_from_acc <= 0;
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ri_from_acc_delay <= 0;
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end else begin
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if (d10) begin
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ri_dist_from_stor <= 0;
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end else if (ri_dist) begin
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ri_dist_from_stor <= 1;
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end
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if (d10 | end_acc_dist_ri) begin
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dist_regen_ctl <= 0;
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end else if (ri_dist | start_acc_dist_ri) begin
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dist_regen_ctl <= 1;
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end
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if (acc_dist_ri) begin
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ri_from_acc_delay <= 1;
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end else if (ri_from_acc_delay) begin
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ri_from_acc_delay <= 0;
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ri_from_acc <= 1;
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end else begin
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ri_from_acc <= 0;
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end
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end;
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//-----------------------------------------------------------------------------
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// D
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//-----------------------------------------------------------------------------
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always @(posedge dp)
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digits[ontime_idx] <= ri_dist_from_stor? selected_storage
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: ri_from_acc? acc_ontime
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: ontime_out;
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digit_pulse bk_sig (rst, dp, ~dist_regen_ctl, 1'b1, dist_back_sig);
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endmodule
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