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[/] [i650/] [trunk/] [rtl/] [error_stop.v] - Blame information for rev 26

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1 23 eightycc
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// IBM 650 Reconstruction in Verilog (i650)
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// 
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// This file is part of the IBM 650 Reconstruction in Verilog (i650) project
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// http:////www.opencores.org/project,i650
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//
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// Description: Error stop and sense controls.
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// 
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// Additional Comments: See US 2959351, Fig. 79.
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//
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// Copyright (c) 2015 Robert Abeles
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//
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// This source file is free software; you can redistribute it
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// and/or modify it under the terms of the GNU Lesser General
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// Public License as published by the Free Software Foundation;
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// either version 2.1 of the License, or (at your option) any
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// later version.
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//
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// This source is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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// PURPOSE.  See the GNU Lesser General Public License for more
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// details.
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//
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// You should have received a copy of the GNU Lesser General
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// Public License along with this source; if not, download it
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// from http://www.opencores.org/lgpl.shtml
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//////////////////////////////////////////////////////////////////////////////////
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`include "defines.v"
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module error_stop (
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    input rst,
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    input ap, dp,
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    input dxu, d10, wl,
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    input err_restart_sw, err_reset, err_sense_reset, clock_err_sig,
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          err_stop_sig, restart_reset_busy,
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    output err_sense_light,
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    output reg err_stop_ed0u, err_sense_restart, restart_reset
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    );
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   reg err_stop, err_sense;
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   //-----------------------------------------------------------------------------
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   //  The err_sense flip-flop does nothing but control a light.
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   //-----------------------------------------------------------------------------
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   assign err_sense_light = err_sense;
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   always @(posedge ap)
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      if      (rst)                       err_sense <= 0;
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      else if (err_sense_reset)           err_sense <= 0;
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      else if (err_stop & err_restart_sw) err_sense <= 1;
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   //-----------------------------------------------------------------------------
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   // This FSM controls the error stop / error restart process.
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   //-----------------------------------------------------------------------------
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   reg [0:2] state;
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   `define restart_idle 3'd0
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   `define restart_1    3'd1
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   `define restart_2    3'd2
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   `define restart_3    3'd3
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   `define restart_4    3'd4
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   `define restart_5    3'd5
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   `define restart_6    3'd6
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   always @(posedge dp)
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      if (rst) begin
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         err_sense_restart <= 0;
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         restart_reset     <= 0;
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         err_stop          <= 0;
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         err_stop_ed0u     <= 0;
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         state             <= `restart_idle;
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      end else
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         case (state)
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            `restart_idle:    // start state, transition on external err signal
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                              // error restart switch selects next state
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               if (err_reset)
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                  err_stop <= 0;
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               else if (~err_stop & (clock_err_sig | err_stop_sig)) begin
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                  err_stop <= 1;
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                  if (err_restart_sw)
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                     state <= `restart_1;
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                  else
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                     state <= `restart_5;
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               end
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            `restart_1:       // >>>error_sense switch position<<<
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                              // wait for dxu
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                              // signal console to begin restart reset
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                              // turn off run latch
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               if (dxu) begin
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                  restart_reset <= 1;
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                  err_stop_ed0u <= 1;
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                  state <= `restart_2;
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               end
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            `restart_2: begin // wait for restart reset to start
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               err_stop_ed0u <= 0;
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               if (restart_reset_busy) begin
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                  restart_reset <= 0;
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                  state <= `restart_3;
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               end
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            end
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            `restart_3:       // wait for end of restart reset
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                              // turn on run latch
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               if (~restart_reset_busy & wl & d10) begin
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                  err_sense_restart <= 1;
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                  err_stop <= 0;
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                  state <= `restart_4;
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               end
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            `restart_4: begin
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               err_sense_restart <= 0;
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               state <= `restart_idle;
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            end
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            `restart_5:       // >>>error_stop switch position<<<
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                              // turn off run latch
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               if (dxu) begin
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                  err_stop_ed0u <= 1;
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                  state <= `restart_6;
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               end
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            `restart_6: begin
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               err_stop_ed0u <= 0;
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               state <= `restart_idle;
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            end
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         endcase;
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endmodule

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