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eightycc |
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// IBM 650 Reconstruction in Verilog (i650)
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//
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// This file is part of the IBM 650 Reconstruction in Verilog (i650) project
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// http:////www.opencores.org/project,i650
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//
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// Description: General storage.
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//
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// Additional Comments: Drum storage is implemented as an array of 24000 5-bit
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// digits. An array address is formed by decoding the static portion of the
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// bi-quinary address into an origin (a multiple of 600), then adding the
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// dynamic portion of the address (range 0..599).
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//
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// Copyright (c) 2015 Robert Abeles
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//
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// This source file is free software; you can redistribute it
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// and/or modify it under the terms of the GNU Lesser General
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// Public License as published by the Free Software Foundation;
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// either version 2.1 of the License, or (at your option) any
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// later version.
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//
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// This source is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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// PURPOSE. See the GNU Lesser General Public License for more
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// details.
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//
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// You should have received a copy of the GNU Lesser General
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// Public License along with this source; if not, download it
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// from http://www.opencores.org/lgpl.shtml
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//////////////////////////////////////////////////////////////////////////////////
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`include "defines.v"
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module gen_store (
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input rst,
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input ap, dp,
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input write_gate,
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input [0:6] addr_th, addr_h, addr_t,
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input [0:9] dynamic_addr,
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input [0:4] gs_in,
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input [0:14] console_ram_addr,
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input console_read_gs, console_write_gs,
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output reg[0:4] gs_out,
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output double_write, no_write
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);
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reg [0:4] gs_mem [0:32767]; // Rounded size up from 24000 to next 2^n.
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//-----------------------------------------------------------------------------
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//
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//-----------------------------------------------------------------------------
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wire [0:14] band_addr, gs_addr, gs_addr_early;
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ram_band_addr rba(addr_th, addr_h, addr_t, band_addr);
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wire console_access = console_read_gs | console_write_gs;
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assign gs_addr = console_access? console_ram_addr : (band_addr + dynamic_addr);
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assign gs_addr_early = (band_addr + ((dynamic_addr + 1) % 600)) % 32768;
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assign double_write = 0;
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assign no_write = 0;
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always @(posedge ap) begin
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if (rst) begin
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gs_out <= `biq_blank;
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end else begin
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gs_out <= gs_mem[gs_addr];
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end
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end;
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always @(posedge dp) begin
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if (write_gate)
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gs_mem[gs_addr_early] <= gs_in;
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end;
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endmodule
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