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eightycc |
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// IBM 650 Reconstruction in Verilog (i650)
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//
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// This file is part of the IBM 650 Reconstruction in Verilog (i650) project
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// http:////www.opencores.org/project,i650
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//
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// Description: Operation code register.
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//
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// Additional Comments: See US 2959351, Fig. 69.
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//
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// Copyright (c) 2015 Robert Abeles
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//
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// This source file is free software; you can redistribute it
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// and/or modify it under the terms of the GNU Lesser General
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// Public License as published by the Free Software Foundation;
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// either version 2.1 of the License, or (at your option) any
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// later version.
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//
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// This source is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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// PURPOSE. See the GNU Lesser General Public License for more
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// details.
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//
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// You should have received a copy of the GNU Lesser General
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// Public License along with this source; if not, download it
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// from http://www.opencores.org/lgpl.shtml
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//////////////////////////////////////////////////////////////////////////////////
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`include "defines.v"
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module op_reg (
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input rst,
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input cp,
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input d0, d9, d10, d1_d5, d5_dx,
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input restart_a, restart_b, d_alt, i_alt, tlu_band_change, man_prog_reset,
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input [0:6] prog_step_ped,
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output reg[0:6] opreg_t, opreg_u,
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output ri_addr_reg
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);
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wire op_reg_reset;
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assign ri_addr_reg = (d_alt & restart_b & d5_dx)
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| (i_alt & restart_b & d1_d5)
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| (tlu_band_change & d1_d5);
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assign op_reg_reset = man_prog_reset | restart_a | (tlu_band_change & d0);
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// reading the program step pedistal, so must wait for c phase
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always @(posedge cp)
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if (rst) begin
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opreg_t <= `biq_blank;
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opreg_u <= `biq_blank;
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end else if (op_reg_reset) begin
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opreg_t <= `biq_blank;
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opreg_u <= `biq_blank;
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end else if (ri_addr_reg) begin
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if (d9)
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opreg_u <= prog_step_ped;
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if (d10)
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opreg_t <= prog_step_ped;
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end;
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endmodule
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