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[/] [i650/] [trunk/] [rtl/] [operator_ctl.v] - Blame information for rev 10

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// IBM 650 Reconstruction in Verilog (i650)
// 
// This file is part of the IBM 650 Reconstruction in Verilog (i650) project
// http:////www.opencores.org/project,i650
//
// Description: Operator console and external control interface.
// 
// Additional Comments: See US 2959351, Fig. 75, 76, 76 and 77. Also implements
//  a simple command-based control interface.
//
// Copyright (c) 2015 Robert Abeles
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE.  See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, download it
// from http://www.opencores.org/lgpl.shtml
//////////////////////////////////////////////////////////////////////////////////
`include "defines.v"
 
module operator_ctl (
      input rst,
      input ap, dp,
      input dx, d0, d1, d2, d3, d4, d5, d6, d10,
      input wu, hp,
      input [0:3] early_idx, ontime_idx,
 
      input [0:6] cmd_digit_in, io_buffer_in,
      input [0:5] command,
 
      output reg[0:6] data_out, addr_out,
      output reg console_to_addr,
      output reg[0:14] gs_ram_addr,
      output reg read_gs, write_gs,
      output reg pgm_start, pgm_stop, err_reset, err_sense_reset,
      output run_control, half_or_pgm_stop, ri_storage, ro_storage,
             storage_control,
      output reg man_pgm_reset, man_acc_reset, set_8000, reset_8000,
 
      output reg[0:6] cmd_digit_out,
      output reg busy, digit_ready,
      output reg punch_card, read_card, card_digit_ready
   );
 
   //-----------------------------------------------------------------------------
   // Operator console switch settings
   //-----------------------------------------------------------------------------
   reg pgm_sw_stop, pgm_sw_run,
       half_cycle_sw_run, half_cycle_sw_half,
       ctl_sw_addr_stop, ctl_sw_run, ctl_sw_manual,
       disp_sw_lacc, disp_sw_uacc, disp_sw_dist, disp_sw_pgm,
       disp_sw_ri, disp_sw_ro,
       ovflw_sw_stop, ovflw_sw_sense, err_sw_stop, err_sw_sense;
   reg [0:6] storage_entry_sw [0:15];
   reg [0:6] addr_sel_sw [0:3];
   assign run_control = disp_sw_lacc | disp_sw_uacc | disp_sw_dist | disp_sw_pgm;
   assign half_or_pgm_stop = half_cycle_sw_half | pgm_stop;
   assign ri_storage = disp_sw_ri;
   assign ro_storage = disp_sw_ro;
   assign storage_control = run_control | disp_sw_ro;
 
   reg do_power_on_reset, do_reset_console, do_err_reset, do_err_sense_reset,
       do_pgm_reset, do_acc_reset;
   reg [0:5] state;
 
   reg [0:6] gs_addr_th, gs_addr_h, gs_addr_t, gs_addr_u;
   wire [0:14] gs_band_addr;
   wire [0:9] gs_word_offset;
   ram_band_addr rba(gs_addr_th, gs_addr_h, gs_addr_t, gs_band_addr);
   ram_word_offset rwo(gs_addr_t, gs_addr_u, gs_word_offset);
   wire [0:14] gs_word_addr = gs_band_addr + gs_word_offset;
 
   `define state_idle                  6'd0
 
   `define state_reset_console_1       6'd1
   `define state_reset_console_2       6'd2
   `define state_pgm_reset_1           6'd3
   `define state_pgm_reset_2           6'd4
   `define state_acc_reset_1           6'd5
   `define state_acc_reset_2           6'd6
   `define state_err_reset_1           6'd7
   `define state_err_reset_2           6'd8
   `define state_err_sense_reset_1     6'd9
   `define state_err_sense_reset_2     6'd10
 
   `define state_storage_entry_sw_1    6'd11
   `define state_storage_entry_sw_2    6'd12
   `define state_addr_sel_sw_1         6'd13
   `define state_addr_sel_sw_2         6'd14
 
   `define state_xfer_key_1            6'd15
   `define state_xfer_key_2            6'd16
   `define state_pgm_start_key_1       6'd17
   `define state_pgm_start_key_2       6'd18
   `define state_pgm_stop_key_1        6'd19
   `define state_pgm_stop_key_2        6'd20
 
   `define state_read_gs_1             6'd31
   `define state_read_gs_2             6'd32
   `define state_read_gs_3             6'd33
   `define state_read_gs_4             6'd34
   `define state_read_gs_5             6'd35
 
   //-----------------------------------------------------------------------------
   // Operator console state machine
   //-----------------------------------------------------------------------------
   always @(posedge rst, posedge dp) begin
      if (rst) begin
         console_to_addr  <= 0;
         pgm_start        <= 0;
         pgm_stop         <= 0;
         err_reset        <= 0;
         err_sense_reset  <= 0;
         man_pgm_reset    <= 0;
         man_acc_reset    <= 0;
         set_8000         <= 0;
         reset_8000       <= 0;
 
         // reset console switches
         pgm_sw_stop      <= 0;
         pgm_sw_run       <= 1;
         ctl_sw_addr_stop <= 0;
         ctl_sw_run       <= 1;
         ctl_sw_manual    <= 0;
         disp_sw_lacc     <= 0;
         disp_sw_uacc     <= 0;
         disp_sw_dist     <= 1;
         disp_sw_pgm     <= 0;
         disp_sw_ri       <= 0;
         disp_sw_ro       <= 0;
         ovflw_sw_stop    <= 1;
         ovflw_sw_sense   <= 0;
         err_sw_stop      <= 1;
         err_sw_sense     <= 0;
 
         state         <= `state_idle;
         busy          <= 1;
         digit_ready   <= 0;
         cmd_digit_out <= `biq_blank;
 
         do_power_on_reset  <= 1;
         do_reset_console   <= 0;
         do_err_reset       <= 0;
         do_err_sense_reset <= 0;
         do_pgm_reset       <= 0;
         do_acc_reset       <= 0;
 
         gs_ram_addr        <= 15'd0;
         read_gs            <= 0;
         write_gs           <= 0;
      end else begin
         case (state)
            `state_idle: begin
               case (command)
                  `cmd_none: begin
                     if (do_power_on_reset) begin
                        do_power_on_reset  <= 0;
                        do_reset_console   <= 1;
                        do_pgm_reset       <= 1;
                        do_acc_reset       <= 1;
                        do_err_reset       <= 1;
                        do_err_sense_reset <= 1;
                     end else if (do_reset_console) begin
                        do_reset_console   <= 0;
                        state <= `state_reset_console_1;
                     end else if (do_pgm_reset) begin
                        do_pgm_reset       <= 0;
                        state <= `state_pgm_reset_1;
                     end else if (do_acc_reset) begin
                        do_acc_reset       <= 0;
                        man_acc_reset      <= 1;
                        state <= `state_acc_reset_1;
                     end else if (do_err_reset) begin
                        do_err_reset       <= 0;
                        err_reset          <= 1;
                        state <= `state_err_reset_1;
                     end else if (do_err_sense_reset) begin
                        do_err_sense_reset <= 0;
                        err_sense_reset <= 1;
                        state <= `state_err_sense_reset_1;
                     end else begin
                        busy <= 0;
                        digit_ready <= 0;
                     end
                  end
 
                  `cmd_pgm_sw_stop: begin
                     busy <= 1;
                     pgm_sw_stop <= 1;
                     pgm_sw_run  <= 0;
                  end
 
                  `cmd_pgm_sw_run: begin
                     busy <= 1;
                     pgm_sw_stop <= 0;
                     pgm_sw_run  <= 1;
                  end
 
                  `cmd_half_cycle_sw_run: begin
                     busy <= 1;
                     half_cycle_sw_run  <= 1;
                     half_cycle_sw_half <= 0;
                  end
 
                  `cmd_half_cycle_sw_half: begin
                     busy <= 1;
                     half_cycle_sw_run  <= 0;
                     half_cycle_sw_half <= 1;
                  end
 
                  `cmd_ctl_sw_addr_stop: begin
                     busy <= 1;
                     ctl_sw_addr_stop <= 1;
                     ctl_sw_run       <= 0;
                     ctl_sw_manual    <= 0;
                  end
 
                  `cmd_ctl_sw_run: begin
                     busy <= 1;
                     ctl_sw_addr_stop <= 0;
                     ctl_sw_run       <= 1;
                     ctl_sw_manual    <= 0;
                  end
 
                  `cmd_ctl_sw_manual: begin
                     busy <= 1;
                     ctl_sw_addr_stop <= 0;
                     ctl_sw_run       <= 0;
                     ctl_sw_manual    <= 1;
                  end
 
                  `cmd_disp_sw_lacc: begin
                     busy <= 1;
                     disp_sw_lacc <= 1;
                     disp_sw_uacc <= 0;
                     disp_sw_dist <= 0;
                     disp_sw_pgm <= 0;
                     disp_sw_ri   <= 0;
                     disp_sw_ro   <= 0;
                  end
 
                  `cmd_disp_sw_uacc: begin
                     busy <= 1;
                     disp_sw_lacc <= 0;
                     disp_sw_uacc <= 1;
                     disp_sw_dist <= 0;
                     disp_sw_pgm <= 0;
                     disp_sw_ri   <= 0;
                     disp_sw_ro   <= 0;
                  end
 
                  `cmd_disp_sw_dist: begin
                     busy <= 1;
                     disp_sw_lacc <= 0;
                     disp_sw_uacc <= 0;
                     disp_sw_dist <= 1;
                     disp_sw_pgm <= 0;
                     disp_sw_ri   <= 0;
                     disp_sw_ro   <= 0;
                  end
 
                  `cmd_disp_sw_prog: begin
                     busy <= 1;
                     disp_sw_lacc <= 0;
                     disp_sw_uacc <= 0;
                     disp_sw_dist <= 0;
                     disp_sw_pgm <= 1;
                     disp_sw_ri   <= 0;
                     disp_sw_ro   <= 0;
                  end
 
                  `cmd_disp_sw_ri: begin
                     busy <= 1;
                     disp_sw_lacc <= 0;
                     disp_sw_uacc <= 0;
                     disp_sw_dist <= 0;
                     disp_sw_pgm <= 0;
                     disp_sw_ri   <= 1;
                     disp_sw_ro   <= 0;
                  end
 
                  `cmd_disp_sw_ro: begin
                     busy <= 1;
                     disp_sw_lacc <= 0;
                     disp_sw_uacc <= 0;
                     disp_sw_dist <= 0;
                     disp_sw_pgm <= 0;
                     disp_sw_ri   <= 0;
                     disp_sw_ro   <= 1;
                  end
 
                  `cmd_ovflw_sw_stop: begin
                     busy <= 1;
                     ovflw_sw_stop  <= 1;
                     ovflw_sw_sense <= 0;
                  end
 
                  `cmd_ovflw_sw_sense: begin
                     busy <= 1;
                     ovflw_sw_stop  <= 0;
                     ovflw_sw_sense <= 1;
                  end
 
                  `cmd_err_sw_stop: begin
                     busy <= 1;
                     err_sw_stop  <= 1;
                     err_sw_sense <= 0;
                  end
 
                  `cmd_err_sw_sense: begin
                     busy <= 1;
                     err_sw_stop  <= 0;
                     err_sw_sense <= 1;
                  end
 
                  `cmd_storage_entry_sw: begin
                     busy <= 1;
                     state <= `state_storage_entry_sw_1;
                  end
 
                  `cmd_addr_sel_sw: begin
                     busy <= 1;
                     state <= `state_addr_sel_sw_1;
                  end
 
                  `cmd_xfer_key: begin
                     if (ctl_sw_manual) begin
                        busy <= 1;
                        state <= `state_xfer_key_1;
                     end
                  end
 
                  `cmd_pgm_start_key: begin
                     busy <= 1;
                     state <= `state_pgm_start_key_1;
                  end
 
                  `cmd_pgm_stop_key: begin
                     busy <= 1;
                     pgm_stop <= 1;
                     state <= `state_pgm_stop_key_1;
                  end
 
                  `cmd_pgm_reset_key: begin
                     do_pgm_reset <= 1;
                     do_err_reset <= 1;
                  end
 
                  `cmd_comp_reset_key: begin
                     do_pgm_reset <= 1;
                     do_acc_reset <= 1;
                     do_err_reset <= 1;
                  end
 
                  `cmd_acc_reset_key: begin
                     do_acc_reset <= 1;
                     do_err_reset <= 1;
                  end
 
                  `cmd_err_reset_key: begin
                     do_err_reset <= 1;
                  end
 
                  `cmd_err_sense_reset_key: begin
                     do_err_sense_reset <= 1;
                  end
 
                  //--------------------------------------------------------------
                  // Read from general storage:
                  //    --> 4 digits address, little-endian
                  //    <-- 1 digit sign, 10 digits, little-endian
                  // 0 : Ignore if CPU not stopped
                  //     Accept low-order address digit
                  // 1 : Accept remaining address digits
                  // 2 : Calculate word origin in gs RAM
                  //     Validate address
                  //     console_read_gs <= 1;
                  // 3 : Send gs-early digit to out
                  //     digit_ready <= 1;
                  // 4 : digit_ready <= 0;
                  //--------------------------------------------------------------
                  `cmd_read_gs: begin
                     if (ctl_sw_manual) begin
                        busy <= 1;
                        state <= `state_read_gs_1;
                     end
                  end
 
 
                  `cmd_write_gs: begin
                  end
 
                  `cmd_read_acc: begin
                  end
 
                  `cmd_read_dist: begin
                  end
 
                  `cmd_read_prog: begin
                  end
 
                  // 0 : Ignore if not in manual
                  //     Clear gs_ram_addr
                  // 1 : Synchronize with d10
                  //     Turn on console_write_gs
                  // 2 : Put a digit:
                  //     dx: blank
                  //     d0: minus
                  //     d1-d10: zero
                  //     gs_ram_addr++
                  `cmd_clear_gs: begin
 
                  end
 
                  `cmd_load_gs: begin
                  end
 
                  `cmd_dump_gs: begin
                  end
 
                  `cmd_power_on_reset: begin
                  end
 
                  `cmd_reset_console: begin
                  end
 
               endcase;
            end
 
            // Reset console            
            `state_reset_console_1: begin
               if (d10) state <= `state_reset_console_2;
            end
 
            `state_reset_console_2: begin
               storage_entry_sw[ontime_idx] <= d0? `biq_plus : `biq_0;
               addr_sel_sw[ontime_idx[2:3]] <= `biq_0;
               if (d10) state <= `state_idle;
            end
 
            // Program reset key press
            `state_pgm_reset_1: begin
               if (wu & d10) begin
                  man_pgm_reset <= 1;
                  state <= `state_pgm_reset_2;
               end
            end
 
            `state_pgm_reset_2: begin
               if (wu & d10) begin
                  man_pgm_reset <= 0;
                  state <= `state_idle;
               end
            end
 
            // Accumulator reset key press
            `state_acc_reset_1: begin
               if (wu & d10) begin
                  man_acc_reset <= 1;
                  state <= `state_acc_reset_2;
               end
            end
 
            `state_acc_reset_2: begin
               if (wu & d10) begin
                  man_acc_reset <= 0;
                  state <= `state_idle;
               end
            end
 
            // Error reset key press
            `state_err_reset_1: begin
               if (wu & d10) begin
                  err_reset <= 1;
                  state <= `state_err_reset_2;
               end
            end
 
            `state_err_reset_2: begin
               if (wu & d10) begin
                  err_reset <= 0;
                  state <= `state_idle;
               end
            end
 
            // Error sense reset key press
            `state_err_sense_reset_1: begin
               if (wu & d10) begin
                  err_sense_reset <= 1;
                  state <= `state_err_sense_reset_2;
               end
            end
 
            `state_err_sense_reset_2: begin
               if (wu & d10) begin
                  err_sense_reset <= 0;
                  state <= `state_idle;
               end
            end
 
            // Set storage entry switches
            `state_storage_entry_sw_1: begin
               if (d0) begin
                  state <= `state_storage_entry_sw_2;
                  digit_ready <= 1;
                  storage_entry_sw[ontime_idx] <= cmd_digit_in;
               end
            end
 
            `state_storage_entry_sw_2: begin
               storage_entry_sw[ontime_idx] <= cmd_digit_in;
               if (d10) begin
                  state <= `state_idle;
                  digit_ready <= 0;
               end
            end
 
            // Set address selection switches
            `state_addr_sel_sw_1: begin
               if (dx) begin
                  state <= `state_addr_sel_sw_2;
                  digit_ready <= 1;
                  addr_sel_sw[ontime_idx[2:3]] <= cmd_digit_in;
               end
            end
 
            `state_addr_sel_sw_2: begin
               addr_sel_sw[ontime_idx[2:3]] <= cmd_digit_in;
               if (d2) begin
                  state <= `state_idle;
                  digit_ready <= 0;
               end
            end
 
            // Transfer key press
            `state_xfer_key_1: begin
               if (d10) begin
                  console_to_addr <= 1;
                  state <= `state_xfer_key_2;
               end
            end
 
            `state_xfer_key_2: begin
               if (d10) begin
                  console_to_addr <= 0;
                  state <= `state_idle;
               end
            end
 
            // Start key press
            `state_pgm_start_key_1: begin
               if (wu & d10) begin
                  pgm_start <= 1;
                  state <= `state_pgm_start_key_2;
               end
            end
 
            `state_pgm_start_key_2: begin
               if (wu & d10) begin
                  pgm_start <= 0;
                  state <= `state_idle;
               end
            end
 
            // Stop key press
            `state_pgm_stop_key_1: begin
               if (hp) state <= `state_pgm_stop_key_2;
            end
 
            `state_pgm_stop_key_2: begin
               if (hp) begin
                  pgm_stop <= 0;
                  state <= `state_idle;
               end
            end
 
            // Read word from general storage
            //    --> 4 digits address, little-endian
            //    <-- 1 digit sign, 10 digits, little-endian
            // 0 : Ignore if CPU not stopped
            //     Accept low-order address digit
            // 1 : Accept remaining address digits
            // 2 : Calculate word origin in gs RAM
            //     Validate address
            //     console_read_gs <= 1;
            // 3 : Send gs-early digit to out
            //     digit_ready <= 1;
            // 4 : digit_ready <= 0;
            `state_read_gs_1: begin
               if (dx) begin
                  state <= `state_read_gs_2;
                  digit_ready <= 1;
                  gs_addr_u <= cmd_digit_in;
               end
            end
 
            `state_read_gs_2: begin
               if (d0) gs_addr_t <= cmd_digit_in;
               else if (d1) gs_addr_h <= cmd_digit_in;
               else if (d2) begin
                  gs_addr_th <= cmd_digit_in;
                  state <= `state_read_gs_3;
                  digit_ready <= 0;
               end
            end
 
            `state_read_gs_3: begin
               gs_ram_addr <= gs_word_addr;
               state <= `state_read_gs_4;
            end
 
            `state_read_gs_4: begin
 
               state <= `state_read_gs_5;
            end
 
         endcase;
      end
   end;
 
   always @(posedge rst, posedge ap) begin
      if (rst) begin
         data_out <= `biq_blank;
         addr_out <= `biq_blank;
      end else begin
         data_out <= d10? `biq_blank : storage_entry_sw[early_idx];
         addr_out <= (d3 | d4 | d5 | d6)? addr_sel_sw[early_idx[2:3]] : `biq_blank;
      end
   end;
 
   always @(posedge rst, posedge ap) begin
      if (rst) begin
         punch_card       <= 0;
         read_card        <= 0;
         card_digit_ready <= 0;
      end
   end;
 
endmodule

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[/] [i650/] [trunk/] [rtl/] [operator_ctl.v] - Blame information for rev 10

Line No.	Rev	Author	Line
1	7	eightycc	`timescale 1ns / 1ps
2			`//////////////////////////////////////////////////////////////////////////////////`
3			`// IBM 650 Reconstruction in Verilog (i650)`
4			`//`
5			`// This file is part of the IBM 650 Reconstruction in Verilog (i650) project`
6			`// http:////www.opencores.org/project,i650`
7			`//`
8			`// Description: Operator console and external control interface.`
9			`//`
10			`// Additional Comments: See US 2959351, Fig. 75, 76, 76 and 77. Also implements`
11			`// a simple command-based control interface.`
12			`//`
13			`// Copyright (c) 2015 Robert Abeles`
14			`//`
15			`// This source file is free software; you can redistribute it`
16			`// and/or modify it under the terms of the GNU Lesser General`
17			`// Public License as published by the Free Software Foundation;`
18			`// either version 2.1 of the License, or (at your option) any`
19			`// later version.`
20			`//`
21			`// This source is distributed in the hope that it will be`
22			`// useful, but WITHOUT ANY WARRANTY; without even the implied`
23			`// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR`
24			`// PURPOSE. See the GNU Lesser General Public License for more`
25			`// details.`
26			`//`
27			`// You should have received a copy of the GNU Lesser General`
28			`// Public License along with this source; if not, download it`
29			`// from http://www.opencores.org/lgpl.shtml`
30			`//////////////////////////////////////////////////////////////////////////////////`
31			`include "defines.v"
32
33			`module operator_ctl (`
34			`input rst,`
35			`input ap, dp,`
36			`input dx, d0, d1, d2, d3, d4, d5, d6, d10,`
37			`input wu, hp,`
38			`input [0:3] early_idx, ontime_idx,`
39
40			`input [0:6] cmd_digit_in, io_buffer_in,`
41			`input [0:5] command,`
42
43			`output reg[0:6] data_out, addr_out,`
44			`output reg console_to_addr,`
45			`output reg[0:14] gs_ram_addr,`
46	10	eightycc	`output reg read_gs, write_gs,`
47	7	eightycc	`output reg pgm_start, pgm_stop, err_reset, err_sense_reset,`
48			`output run_control, half_or_pgm_stop, ri_storage, ro_storage,`
49			`storage_control,`
50			`output reg man_pgm_reset, man_acc_reset, set_8000, reset_8000,`
51
52			`output reg[0:6] cmd_digit_out,`
53			`output reg busy, digit_ready,`
54			`output reg punch_card, read_card, card_digit_ready`
55			`);`
56
57			`//-----------------------------------------------------------------------------`
58			`// Operator console switch settings`
59			`//-----------------------------------------------------------------------------`
60			`reg pgm_sw_stop, pgm_sw_run,`
61			`half_cycle_sw_run, half_cycle_sw_half,`
62			`ctl_sw_addr_stop, ctl_sw_run, ctl_sw_manual,`
63			`disp_sw_lacc, disp_sw_uacc, disp_sw_dist, disp_sw_pgm,`
64			`disp_sw_ri, disp_sw_ro,`
65			`ovflw_sw_stop, ovflw_sw_sense, err_sw_stop, err_sw_sense;`
66			`reg [0:6] storage_entry_sw [0:15];`
67			`reg [0:6] addr_sel_sw [0:3];`
68			`assign run_control = disp_sw_lacc \| disp_sw_uacc \| disp_sw_dist \| disp_sw_pgm;`
69			`assign half_or_pgm_stop = half_cycle_sw_half \| pgm_stop;`
70			`assign ri_storage = disp_sw_ri;`
71			`assign ro_storage = disp_sw_ro;`
72			`assign storage_control = run_control \| disp_sw_ro;`
73
74			`reg do_power_on_reset, do_reset_console, do_err_reset, do_err_sense_reset,`
75			`do_pgm_reset, do_acc_reset;`
76			`reg [0:5] state;`
77
78			`reg [0:6] gs_addr_th, gs_addr_h, gs_addr_t, gs_addr_u;`
79	9	eightycc	`wire [0:14] gs_band_addr;`
80	10	eightycc	`wire [0:9] gs_word_offset;`
81	9	eightycc	`ram_band_addr rba(gs_addr_th, gs_addr_h, gs_addr_t, gs_band_addr);`
82	7	eightycc	`ram_word_offset rwo(gs_addr_t, gs_addr_u, gs_word_offset);`
83			`wire [0:14] gs_word_addr = gs_band_addr + gs_word_offset;`
84
85			`define state_idle 6'd0
86
87			`define state_reset_console_1 6'd1
88			`define state_reset_console_2 6'd2
89			`define state_pgm_reset_1 6'd3
90			`define state_pgm_reset_2 6'd4
91			`define state_acc_reset_1 6'd5
92			`define state_acc_reset_2 6'd6
93			`define state_err_reset_1 6'd7
94			`define state_err_reset_2 6'd8
95			`define state_err_sense_reset_1 6'd9
96			`define state_err_sense_reset_2 6'd10
97
98			`define state_storage_entry_sw_1 6'd11
99			`define state_storage_entry_sw_2 6'd12
100			`define state_addr_sel_sw_1 6'd13
101			`define state_addr_sel_sw_2 6'd14
102
103			`define state_xfer_key_1 6'd15
104			`define state_xfer_key_2 6'd16
105			`define state_pgm_start_key_1 6'd17
106			`define state_pgm_start_key_2 6'd18
107			`define state_pgm_stop_key_1 6'd19
108			`define state_pgm_stop_key_2 6'd20
109
110			`define state_read_gs_1 6'd31
111			`define state_read_gs_2 6'd32
112			`define state_read_gs_3 6'd33
113			`define state_read_gs_4 6'd34
114	10	eightycc	`define state_read_gs_5 6'd35
115	7	eightycc
116			`//-----------------------------------------------------------------------------`
117			`// Operator console state machine`
118			`//-----------------------------------------------------------------------------`
119			`always @(posedge rst, posedge dp) begin`
120			`if (rst) begin`
121			`console_to_addr <= 0;`
122			`pgm_start <= 0;`
123			`pgm_stop <= 0;`
124			`err_reset <= 0;`
125			`err_sense_reset <= 0;`
126			`man_pgm_reset <= 0;`
127			`man_acc_reset <= 0;`
128			`set_8000 <= 0;`
129			`reset_8000 <= 0;`
130
131			`// reset console switches`
132			`pgm_sw_stop <= 0;`
133			`pgm_sw_run <= 1;`
134			`ctl_sw_addr_stop <= 0;`
135			`ctl_sw_run <= 1;`
136			`ctl_sw_manual <= 0;`
137			`disp_sw_lacc <= 0;`
138			`disp_sw_uacc <= 0;`
139			`disp_sw_dist <= 1;`
140			`disp_sw_pgm <= 0;`
141			`disp_sw_ri <= 0;`
142			`disp_sw_ro <= 0;`
143			`ovflw_sw_stop <= 1;`
144			`ovflw_sw_sense <= 0;`
145			`err_sw_stop <= 1;`
146			`err_sw_sense <= 0;`
147
148			state <= `state_idle;
149			`busy <= 1;`
150			`digit_ready <= 0;`
151			cmd_digit_out <= `biq_blank;
152
153			`do_power_on_reset <= 1;`
154			`do_reset_console <= 0;`
155			`do_err_reset <= 0;`
156			`do_err_sense_reset <= 0;`
157			`do_pgm_reset <= 0;`
158			`do_acc_reset <= 0;`
159
160			`gs_ram_addr <= 15'd0;`
161	9	eightycc	`read_gs <= 0;`
162	10	eightycc	`write_gs <= 0;`
163	7	eightycc	`end else begin`
164			`case (state)`
165			`state_idle: begin
166			`case (command)`
167			`cmd_none: begin
168			`if (do_power_on_reset) begin`
169			`do_power_on_reset <= 0;`
170			`do_reset_console <= 1;`
171			`do_pgm_reset <= 1;`
172			`do_acc_reset <= 1;`
173			`do_err_reset <= 1;`
174			`do_err_sense_reset <= 1;`
175			`end else if (do_reset_console) begin`
176			`do_reset_console <= 0;`
177			state <= `state_reset_console_1;
178			`end else if (do_pgm_reset) begin`
179			`do_pgm_reset <= 0;`
180			state <= `state_pgm_reset_1;
181			`end else if (do_acc_reset) begin`
182			`do_acc_reset <= 0;`
183			`man_acc_reset <= 1;`
184			state <= `state_acc_reset_1;
185			`end else if (do_err_reset) begin`
186			`do_err_reset <= 0;`
187			`err_reset <= 1;`
188			state <= `state_err_reset_1;
189			`end else if (do_err_sense_reset) begin`
190			`do_err_sense_reset <= 0;`
191			`err_sense_reset <= 1;`
192			state <= `state_err_sense_reset_1;
193			`end else begin`
194			`busy <= 0;`
195			`digit_ready <= 0;`
196			`end`
197			`end`
198
199			`cmd_pgm_sw_stop: begin
200			`busy <= 1;`
201			`pgm_sw_stop <= 1;`
202			`pgm_sw_run <= 0;`
203			`end`
204
205			`cmd_pgm_sw_run: begin
206			`busy <= 1;`
207			`pgm_sw_stop <= 0;`
208			`pgm_sw_run <= 1;`
209			`end`
210
211			`cmd_half_cycle_sw_run: begin
212			`busy <= 1;`
213			`half_cycle_sw_run <= 1;`
214			`half_cycle_sw_half <= 0;`
215			`end`
216
217			`cmd_half_cycle_sw_half: begin
218			`busy <= 1;`
219			`half_cycle_sw_run <= 0;`
220			`half_cycle_sw_half <= 1;`
221			`end`
222
223			`cmd_ctl_sw_addr_stop: begin
224			`busy <= 1;`
225			`ctl_sw_addr_stop <= 1;`
226			`ctl_sw_run <= 0;`
227			`ctl_sw_manual <= 0;`
228			`end`
229
230			`cmd_ctl_sw_run: begin
231			`busy <= 1;`
232			`ctl_sw_addr_stop <= 0;`
233			`ctl_sw_run <= 1;`
234			`ctl_sw_manual <= 0;`
235			`end`
236
237			`cmd_ctl_sw_manual: begin
238			`busy <= 1;`
239			`ctl_sw_addr_stop <= 0;`
240			`ctl_sw_run <= 0;`
241			`ctl_sw_manual <= 1;`
242			`end`
243
244			`cmd_disp_sw_lacc: begin
245			`busy <= 1;`
246			`disp_sw_lacc <= 1;`
247			`disp_sw_uacc <= 0;`
248			`disp_sw_dist <= 0;`
249			`disp_sw_pgm <= 0;`
250			`disp_sw_ri <= 0;`
251			`disp_sw_ro <= 0;`
252			`end`
253
254			`cmd_disp_sw_uacc: begin
255			`busy <= 1;`
256			`disp_sw_lacc <= 0;`
257			`disp_sw_uacc <= 1;`
258			`disp_sw_dist <= 0;`
259			`disp_sw_pgm <= 0;`
260			`disp_sw_ri <= 0;`
261			`disp_sw_ro <= 0;`
262			`end`
263
264			`cmd_disp_sw_dist: begin
265			`busy <= 1;`
266			`disp_sw_lacc <= 0;`
267			`disp_sw_uacc <= 0;`
268			`disp_sw_dist <= 1;`
269			`disp_sw_pgm <= 0;`
270			`disp_sw_ri <= 0;`
271			`disp_sw_ro <= 0;`
272			`end`
273
274			`cmd_disp_sw_prog: begin
275			`busy <= 1;`
276			`disp_sw_lacc <= 0;`
277			`disp_sw_uacc <= 0;`
278			`disp_sw_dist <= 0;`
279			`disp_sw_pgm <= 1;`
280			`disp_sw_ri <= 0;`
281			`disp_sw_ro <= 0;`
282			`end`
283
284			`cmd_disp_sw_ri: begin
285			`busy <= 1;`
286			`disp_sw_lacc <= 0;`
287			`disp_sw_uacc <= 0;`
288			`disp_sw_dist <= 0;`
289			`disp_sw_pgm <= 0;`
290			`disp_sw_ri <= 1;`
291			`disp_sw_ro <= 0;`
292			`end`
293
294			`cmd_disp_sw_ro: begin
295			`busy <= 1;`
296			`disp_sw_lacc <= 0;`
297			`disp_sw_uacc <= 0;`
298			`disp_sw_dist <= 0;`
299			`disp_sw_pgm <= 0;`
300			`disp_sw_ri <= 0;`
301			`disp_sw_ro <= 1;`
302			`end`
303
304			`cmd_ovflw_sw_stop: begin
305			`busy <= 1;`
306			`ovflw_sw_stop <= 1;`
307			`ovflw_sw_sense <= 0;`
308			`end`
309
310			`cmd_ovflw_sw_sense: begin
311			`busy <= 1;`
312			`ovflw_sw_stop <= 0;`
313			`ovflw_sw_sense <= 1;`
314			`end`
315
316			`cmd_err_sw_stop: begin
317			`busy <= 1;`
318			`err_sw_stop <= 1;`
319			`err_sw_sense <= 0;`
320			`end`
321
322			`cmd_err_sw_sense: begin
323			`busy <= 1;`
324			`err_sw_stop <= 0;`
325			`err_sw_sense <= 1;`
326			`end`
327
328			`cmd_storage_entry_sw: begin
329			`busy <= 1;`
330			state <= `state_storage_entry_sw_1;
331			`end`
332
333			`cmd_addr_sel_sw: begin
334			`busy <= 1;`
335			state <= `state_addr_sel_sw_1;
336			`end`
337
338			`cmd_xfer_key: begin
339			`if (ctl_sw_manual) begin`
340			`busy <= 1;`
341			state <= `state_xfer_key_1;
342			`end`
343			`end`
344
345			`cmd_pgm_start_key: begin
346			`busy <= 1;`
347			state <= `state_pgm_start_key_1;
348			`end`
349
350			`cmd_pgm_stop_key: begin
351			`busy <= 1;`
352			`pgm_stop <= 1;`
353			state <= `state_pgm_stop_key_1;
354			`end`
355
356			`cmd_pgm_reset_key: begin
357			`do_pgm_reset <= 1;`
358			`do_err_reset <= 1;`
359			`end`
360
361			`cmd_comp_reset_key: begin
362			`do_pgm_reset <= 1;`
363			`do_acc_reset <= 1;`
364			`do_err_reset <= 1;`
365			`end`
366
367			`cmd_acc_reset_key: begin
368			`do_acc_reset <= 1;`
369			`do_err_reset <= 1;`
370			`end`
371
372			`cmd_err_reset_key: begin
373			`do_err_reset <= 1;`
374			`end`
375
376			`cmd_err_sense_reset_key: begin
377			`do_err_sense_reset <= 1;`
378			`end`
379
380			`//--------------------------------------------------------------`
381			`// Read from general storage:`
382			`// --> 4 digits address, little-endian`
383			`// <-- 1 digit sign, 10 digits, little-endian`
384			`// 0 : Ignore if CPU not stopped`
385			`// Accept low-order address digit`
386			`// 1 : Accept remaining address digits`
387			`// 2 : Calculate word origin in gs RAM`
388			`// Validate address`
389			`// console_read_gs <= 1;`
390			`// 3 : Send gs-early digit to out`
391			`// digit_ready <= 1;`
392			`// 4 : digit_ready <= 0;`
393			`//--------------------------------------------------------------`
394			`cmd_read_gs: begin
395			`if (ctl_sw_manual) begin`
396			`busy <= 1;`
397			state <= `state_read_gs_1;
398			`end`
399			`end`
400	10	eightycc
401	9	eightycc
402			`cmd_write_gs: begin
403	10	eightycc	`end`
404
405	9	eightycc	`cmd_read_acc: begin
406	10	eightycc	`end`
407
408	9	eightycc	`cmd_read_dist: begin
409	10	eightycc	`end`
410
411	9	eightycc	`cmd_read_prog: begin
412	10	eightycc	`end`
413
414			`// 0 : Ignore if not in manual`
415			`// Clear gs_ram_addr`
416			`// 1 : Synchronize with d10`
417			`// Turn on console_write_gs`
418			`// 2 : Put a digit:`
419			`// dx: blank`
420			`// d0: minus`
421			`// d1-d10: zero`
422			`// gs_ram_addr++`
423	9	eightycc	`cmd_clear_gs: begin
424	10	eightycc
425			`end`
426
427	9	eightycc	`cmd_load_gs: begin
428	10	eightycc	`end`
429
430	9	eightycc	`cmd_dump_gs: begin
431	10	eightycc	`end`
432
433	9	eightycc	`cmd_power_on_reset: begin
434	10	eightycc	`end`
435
436	9	eightycc	`cmd_reset_console: begin
437	10	eightycc	`end`
438	7	eightycc
439			`endcase;`
440			`end`
441
442			`// Reset console`
443			`state_reset_console_1: begin
444			if (d10) state <= `state_reset_console_2;
445			`end`
446
447			`state_reset_console_2: begin
448			storage_entry_sw[ontime_idx] <= d0? `biq_plus : `biq_0;
449			addr_sel_sw[ontime_idx[2:3]] <= `biq_0;
450			if (d10) state <= `state_idle;
451			`end`
452
453			`// Program reset key press`
454			`state_pgm_reset_1: begin
455			`if (wu & d10) begin`
456			`man_pgm_reset <= 1;`
457			state <= `state_pgm_reset_2;
458			`end`
459			`end`
460
461			`state_pgm_reset_2: begin
462			`if (wu & d10) begin`
463			`man_pgm_reset <= 0;`
464			state <= `state_idle;
465			`end`
466			`end`
467
468			`// Accumulator reset key press`
469			`state_acc_reset_1: begin
470			`if (wu & d10) begin`
471			`man_acc_reset <= 1;`
472			state <= `state_acc_reset_2;
473			`end`
474			`end`
475
476			`state_acc_reset_2: begin
477			`if (wu & d10) begin`
478			`man_acc_reset <= 0;`
479			state <= `state_idle;
480			`end`
481			`end`
482
483			`// Error reset key press`
484			`state_err_reset_1: begin
485			`if (wu & d10) begin`
486			`err_reset <= 1;`
487			state <= `state_err_reset_2;
488			`end`
489			`end`
490
491			`state_err_reset_2: begin
492			`if (wu & d10) begin`
493			`err_reset <= 0;`
494			state <= `state_idle;
495			`end`
496			`end`
497
498			`// Error sense reset key press`
499			`state_err_sense_reset_1: begin
500			`if (wu & d10) begin`
501			`err_sense_reset <= 1;`
502			state <= `state_err_sense_reset_2;
503			`end`
504			`end`
505
506			`state_err_sense_reset_2: begin
507			`if (wu & d10) begin`
508			`err_sense_reset <= 0;`
509			state <= `state_idle;
510			`end`
511			`end`
512
513			`// Set storage entry switches`
514			`state_storage_entry_sw_1: begin
515			`if (d0) begin`
516			state <= `state_storage_entry_sw_2;
517			`digit_ready <= 1;`
518			`storage_entry_sw[ontime_idx] <= cmd_digit_in;`
519			`end`
520			`end`
521
522			`state_storage_entry_sw_2: begin
523			`storage_entry_sw[ontime_idx] <= cmd_digit_in;`
524			`if (d10) begin`
525			state <= `state_idle;
526			`digit_ready <= 0;`
527			`end`
528			`end`
529
530			`// Set address selection switches`
531			`state_addr_sel_sw_1: begin
532			`if (dx) begin`
533			state <= `state_addr_sel_sw_2;
534			`digit_ready <= 1;`
535			`addr_sel_sw[ontime_idx[2:3]] <= cmd_digit_in;`
536			`end`
537			`end`
538
539			`state_addr_sel_sw_2: begin
540			`addr_sel_sw[ontime_idx[2:3]] <= cmd_digit_in;`
541			`if (d2) begin`
542			state <= `state_idle;
543			`digit_ready <= 0;`
544			`end`
545			`end`
546
547			`// Transfer key press`
548			`state_xfer_key_1: begin
549			`if (d10) begin`
550			`console_to_addr <= 1;`
551			state <= `state_xfer_key_2;
552			`end`
553			`end`
554
555			`state_xfer_key_2: begin
556			`if (d10) begin`
557			`console_to_addr <= 0;`
558			state <= `state_idle;
559			`end`
560			`end`
561
562			`// Start key press`
563			`state_pgm_start_key_1: begin
564			`if (wu & d10) begin`
565			`pgm_start <= 1;`
566			state <= `state_pgm_start_key_2;
567			`end`
568			`end`
569
570			`state_pgm_start_key_2: begin
571			`if (wu & d10) begin`
572			`pgm_start <= 0;`
573			state <= `state_idle;
574			`end`
575			`end`
576
577			`// Stop key press`
578			`state_pgm_stop_key_1: begin
579			if (hp) state <= `state_pgm_stop_key_2;
580			`end`
581
582			`state_pgm_stop_key_2: begin
583			`if (hp) begin`
584			`pgm_stop <= 0;`
585			state <= `state_idle;
586			`end`
587			`end`
588
589			`// Read word from general storage`
590			`// --> 4 digits address, little-endian`
591			`// <-- 1 digit sign, 10 digits, little-endian`
592			`// 0 : Ignore if CPU not stopped`
593			`// Accept low-order address digit`
594			`// 1 : Accept remaining address digits`
595			`// 2 : Calculate word origin in gs RAM`
596			`// Validate address`
597			`// console_read_gs <= 1;`
598			`// 3 : Send gs-early digit to out`
599			`// digit_ready <= 1;`
600			`// 4 : digit_ready <= 0;`
601			`state_read_gs_1: begin
602			`if (dx) begin`
603			state <= `state_read_gs_2;
604			`digit_ready <= 1;`
605			`gs_addr_u <= cmd_digit_in;`
606			`end`
607			`end`
608
609			`state_read_gs_2: begin
610			`if (d0) gs_addr_t <= cmd_digit_in;`
611			`else if (d1) gs_addr_h <= cmd_digit_in;`
612			`else if (d2) begin`
613			`gs_addr_th <= cmd_digit_in;`
614			state <= `state_read_gs_3;
615			`digit_ready <= 0;`
616			`end`
617			`end`
618
619			`state_read_gs_3: begin
620			`gs_ram_addr <= gs_word_addr;`
621			state <= `state_read_gs_4;
622			`end`
623
624	10	eightycc	`state_read_gs_4: begin
625
626			state <= `state_read_gs_5;
627			`end`
628
629	7	eightycc	`endcase;`
630			`end`
631			`end;`
632
633			`always @(posedge rst, posedge ap) begin`
634			`if (rst) begin`
635			data_out <= `biq_blank;
636			addr_out <= `biq_blank;
637			`end else begin`
638			data_out <= d10? `biq_blank : storage_entry_sw[early_idx];
639			addr_out <= (d3 \| d4 \| d5 \| d6)? addr_sel_sw[early_idx[2:3]] : `biq_blank;
640			`end`
641			`end;`
642
643			`always @(posedge rst, posedge ap) begin`
644			`if (rst) begin`
645			`punch_card <= 0;`
646			`read_card <= 0;`
647			`card_digit_ready <= 0;`
648			`end`
649			`end;`
650
651			`endmodule`