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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// IBM 650 Reconstruction in Verilog (i650)
// 
// This file is part of the IBM 650 Reconstruction in Verilog (i650) project
// http:////www.opencores.org/project,i650
//
// Description: Operator console and external control interface.
// 
// Additional Comments: See US 2959351, Fig. 75, 76, 76 and 77. Also implements
//  a simple command-based control interface.
//
// Copyright (c) 2015 Robert Abeles
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE.  See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, download it
// from http://www.opencores.org/lgpl.shtml
//////////////////////////////////////////////////////////////////////////////////
`include "defines.v"
 
module operator_ctl (
      input rst, clk,
      input ap, dp,
      input dx, d0, d1, d2, d3, d4, d5, d6, d10,
      input wu, hp,
      input [0:3] early_idx, ontime_idx,
 
      input [0:6] cmd_digit_in, io_buffer_in, gs_in,
      input [0:5] command,
 
      output reg[0:6] data_out, addr_out, console_out,
      output reg console_to_addr,
      output reg[0:14] gs_ram_addr,
      output reg read_gs, write_gs,
      output reg pgm_start, pgm_stop, err_reset, err_sense_reset,
      output run_control, half_or_pgm_stop, ri_storage, ro_storage,
             storage_control,
      output reg man_pgm_reset, man_acc_reset, set_8000, reset_8000,
                 hard_reset,
 
      output reg[0:6] cmd_digit_out,
      output reg busy, digit_ready,
      output reg punch_card, read_card, card_digit_ready
   );
 
   //-----------------------------------------------------------------------------
   // Operator console switch settings
   //-----------------------------------------------------------------------------
   reg pgm_sw_stop, pgm_sw_run,
       half_cycle_sw_run, half_cycle_sw_half,
       ctl_sw_addr_stop, ctl_sw_run, ctl_sw_manual,
       disp_sw_lacc, disp_sw_uacc, disp_sw_dist, disp_sw_pgm,
       disp_sw_ri, disp_sw_ro,
       ovflw_sw_stop, ovflw_sw_sense, err_sw_stop, err_sw_sense;
   reg [0:6] storage_entry_sw [0:15];
   reg [0:6] addr_sel_sw [0:3];
   assign run_control = disp_sw_lacc | disp_sw_uacc | disp_sw_dist | disp_sw_pgm;
   assign half_or_pgm_stop = half_cycle_sw_half | pgm_stop;
   assign ri_storage = disp_sw_ri;
   assign ro_storage = disp_sw_ro;
   assign storage_control = run_control | disp_sw_ro;
 
   reg do_power_on_reset, do_reset_console, do_err_reset, do_err_sense_reset,
       do_pgm_reset, do_acc_reset, do_hard_reset, do_clear_drum;
   reg [0:5] state;
 
   reg [0:6] gs_addr_th, gs_addr_h, gs_addr_t, gs_addr_u;
   wire [0:14] gs_band_addr;
   wire [0:9] gs_word_offset;
   ram_band_addr rba(gs_addr_th, gs_addr_h, gs_addr_t, gs_band_addr);
   ram_word_offset rwo(gs_addr_t, gs_addr_u, gs_word_offset);
   wire [0:14] gs_word_addr = gs_band_addr + gs_word_offset;
 
   `define state_idle                  6'd0
 
   `define state_reset_console_1       6'd1
   `define state_reset_console_2       6'd2
   `define state_pgm_reset_1           6'd3
   `define state_pgm_reset_2           6'd4
   `define state_acc_reset_1           6'd5
   `define state_acc_reset_2           6'd6
   `define state_err_reset_1           6'd7
   `define state_err_reset_2           6'd8
   `define state_err_sense_reset_1     6'd9
   `define state_err_sense_reset_2     6'd10
   `define state_hard_reset_1          6'd11
 
   `define state_storage_entry_sw_1    6'd12
   `define state_storage_entry_sw_2    6'd13
   `define state_addr_sel_sw_1         6'd14
   `define state_addr_sel_sw_2         6'd15
 
   `define state_xfer_key_1            6'd16
   `define state_xfer_key_2            6'd17
   `define state_pgm_start_key_1       6'd18
   `define state_pgm_start_key_2       6'd19
   `define state_pgm_stop_key_1        6'd20
   `define state_pgm_stop_key_2        6'd21
 
   `define state_read_gs_1             6'd30
   `define state_read_gs_2             6'd31
   `define state_read_gs_3             6'd32
   `define state_read_gs_4             6'd33
   `define state_read_gs_5             6'd34
 
   `define state_clear_drum_1          6'd50
   `define state_clear_drum_2          6'd51
   `define state_clear_drum_3          6'd52
 
   //-----------------------------------------------------------------------------
   // Operator console state machine
   //-----------------------------------------------------------------------------
   always @(posedge clk) begin
      if (rst) begin
         console_to_addr  <= 0;
         pgm_start        <= 0;
         pgm_stop         <= 0;
         err_reset        <= 0;
         err_sense_reset  <= 0;
         man_pgm_reset    <= 0;
         man_acc_reset    <= 0;
         set_8000         <= 0;
         reset_8000       <= 0;
         hard_reset       <= 0;
 
         // reset console switches
         pgm_sw_stop      <= 0;
         pgm_sw_run       <= 1;
         half_cycle_sw_run <= 1;
         half_cycle_sw_half <= 0;
         ctl_sw_addr_stop <= 0;
         ctl_sw_run       <= 1;
         ctl_sw_manual    <= 0;
         disp_sw_lacc     <= 0;
         disp_sw_uacc     <= 0;
         disp_sw_dist     <= 1;
         disp_sw_pgm     <= 0;
         disp_sw_ri       <= 0;
         disp_sw_ro       <= 0;
         ovflw_sw_stop    <= 1;
         ovflw_sw_sense   <= 0;
         err_sw_stop      <= 1;
         err_sw_sense     <= 0;
 
         state         <= `state_idle;
         busy          <= 1;
         digit_ready   <= 0;
         cmd_digit_out <= `biq_blank;
 
         do_power_on_reset  <= 1;
         do_reset_console   <= 0;
         do_err_reset       <= 0;
         do_err_sense_reset <= 0;
         do_pgm_reset       <= 0;
         do_acc_reset       <= 0;
         do_hard_reset      <= 0;
         do_clear_drum      <= 0;
 
         gs_ram_addr        <= 15'd0;
         read_gs            <= 0;
         write_gs           <= 0;
         console_out        <= `biq_blank;
      end else if (dp) begin
         case (state)
            `state_idle: begin
               case (command)
                  `cmd_none: begin
                     if (do_power_on_reset) begin
                        do_power_on_reset  <= 0;
                        do_reset_console   <= 1;
                        do_pgm_reset       <= 1;
                        do_acc_reset       <= 1;
                        do_err_reset       <= 1;
                        do_err_sense_reset <= 1;
                        do_hard_reset      <= 1;
                        do_clear_drum      <= 1;
                     end else if (do_hard_reset) begin
                        do_hard_reset <= 0;
                        hard_reset <= 1;
                        state <= `state_hard_reset_1;
                     end else if (do_reset_console) begin
                        do_reset_console   <= 0;
                        state <= `state_reset_console_1;
                     end else if (do_clear_drum) begin
                        do_clear_drum <= 0;
                        gs_ram_addr <= 15'd0;
                        state <= `state_clear_drum_1;
                     end else if (do_pgm_reset) begin
                        do_pgm_reset       <= 0;
                        state <= `state_pgm_reset_1;
                     end else if (do_acc_reset) begin
                        do_acc_reset       <= 0;
                        man_acc_reset      <= 1;
                        state <= `state_acc_reset_1;
                     end else if (do_err_reset) begin
                        do_err_reset       <= 0;
                        err_reset          <= 1;
                        state <= `state_err_reset_1;
                     end else if (do_err_sense_reset) begin
                        do_err_sense_reset <= 0;
                        err_sense_reset <= 1;
                        state <= `state_err_sense_reset_1;
                     end else begin
                        busy <= 0;
                        digit_ready <= 0;
                     end
                  end
 
                  `cmd_pgm_sw_stop: begin
                     busy <= 1;
                     pgm_sw_stop <= 1;
                     pgm_sw_run  <= 0;
                  end
 
                  `cmd_pgm_sw_run: begin
                     busy <= 1;
                     pgm_sw_stop <= 0;
                     pgm_sw_run  <= 1;
                  end
 
                  `cmd_half_cycle_sw_run: begin
                     busy <= 1;
                     half_cycle_sw_run  <= 1;
                     half_cycle_sw_half <= 0;
                  end
 
                  `cmd_half_cycle_sw_half: begin
                     busy <= 1;
                     half_cycle_sw_run  <= 0;
                     half_cycle_sw_half <= 1;
                  end
 
                  `cmd_ctl_sw_addr_stop: begin
                     busy <= 1;
                     ctl_sw_addr_stop <= 1;
                     ctl_sw_run       <= 0;
                     ctl_sw_manual    <= 0;
                  end
 
                  `cmd_ctl_sw_run: begin
                     busy <= 1;
                     ctl_sw_addr_stop <= 0;
                     ctl_sw_run       <= 1;
                     ctl_sw_manual    <= 0;
                  end
 
                  `cmd_ctl_sw_manual: begin
                     busy <= 1;
                     ctl_sw_addr_stop <= 0;
                     ctl_sw_run       <= 0;
                     ctl_sw_manual    <= 1;
                  end
 
                  `cmd_disp_sw_lacc: begin
                     busy <= 1;
                     disp_sw_lacc <= 1;
                     disp_sw_uacc <= 0;
                     disp_sw_dist <= 0;
                     disp_sw_pgm <= 0;
                     disp_sw_ri   <= 0;
                     disp_sw_ro   <= 0;
                  end
 
                  `cmd_disp_sw_uacc: begin
                     busy <= 1;
                     disp_sw_lacc <= 0;
                     disp_sw_uacc <= 1;
                     disp_sw_dist <= 0;
                     disp_sw_pgm <= 0;
                     disp_sw_ri   <= 0;
                     disp_sw_ro   <= 0;
                  end
 
                  `cmd_disp_sw_dist: begin
                     busy <= 1;
                     disp_sw_lacc <= 0;
                     disp_sw_uacc <= 0;
                     disp_sw_dist <= 1;
                     disp_sw_pgm <= 0;
                     disp_sw_ri   <= 0;
                     disp_sw_ro   <= 0;
                  end
 
                  `cmd_disp_sw_prog: begin
                     busy <= 1;
                     disp_sw_lacc <= 0;
                     disp_sw_uacc <= 0;
                     disp_sw_dist <= 0;
                     disp_sw_pgm <= 1;
                     disp_sw_ri   <= 0;
                     disp_sw_ro   <= 0;
                  end
 
                  `cmd_disp_sw_ri: begin
                     busy <= 1;
                     disp_sw_lacc <= 0;
                     disp_sw_uacc <= 0;
                     disp_sw_dist <= 0;
                     disp_sw_pgm <= 0;
                     disp_sw_ri   <= 1;
                     disp_sw_ro   <= 0;
                  end
 
                  `cmd_disp_sw_ro: begin
                     busy <= 1;
                     disp_sw_lacc <= 0;
                     disp_sw_uacc <= 0;
                     disp_sw_dist <= 0;
                     disp_sw_pgm <= 0;
                     disp_sw_ri   <= 0;
                     disp_sw_ro   <= 1;
                  end
 
                  `cmd_ovflw_sw_stop: begin
                     busy <= 1;
                     ovflw_sw_stop  <= 1;
                     ovflw_sw_sense <= 0;
                  end
 
                  `cmd_ovflw_sw_sense: begin
                     busy <= 1;
                     ovflw_sw_stop  <= 0;
                     ovflw_sw_sense <= 1;
                  end
 
                  `cmd_err_sw_stop: begin
                     busy <= 1;
                     err_sw_stop  <= 1;
                     err_sw_sense <= 0;
                  end
 
                  `cmd_err_sw_sense: begin
                     busy <= 1;
                     err_sw_stop  <= 0;
                     err_sw_sense <= 1;
                  end
 
                  `cmd_storage_entry_sw: begin
                     busy <= 1;
                     state <= `state_storage_entry_sw_1;
                  end
 
                  `cmd_addr_sel_sw: begin
                     busy <= 1;
                     state <= `state_addr_sel_sw_1;
                  end
 
                  `cmd_xfer_key: begin
                     if (ctl_sw_manual) begin
                        busy <= 1;
                        state <= `state_xfer_key_1;
                     end
                  end
 
                  `cmd_pgm_start_key: begin
                     busy <= 1;
                     state <= `state_pgm_start_key_1;
                  end
 
                  `cmd_pgm_stop_key: begin
                     busy <= 1;
                     pgm_stop <= 1;
                     state <= `state_pgm_stop_key_1;
                  end
 
                  `cmd_pgm_reset_key: begin
                     busy <= 1;
                     do_pgm_reset <= 1;
                     do_err_reset <= 1;
                  end
 
                  `cmd_comp_reset_key: begin
                     busy <= 1;
                     do_pgm_reset <= 1;
                     do_acc_reset <= 1;
                     do_err_reset <= 1;
                  end
 
                  `cmd_acc_reset_key: begin
                     busy <= 1;
                     do_acc_reset <= 1;
                     do_err_reset <= 1;
                  end
 
                  `cmd_err_reset_key: begin
                     busy <= 1;
                     do_err_reset <= 1;
                  end
 
                  `cmd_err_sense_reset_key: begin
                     busy <= 1;
                     do_err_sense_reset <= 1;
                  end
 
                  //--------------------------------------------------------------
                  // Read from general storage:
                  //    --> 4 digits address, little-endian
                  //    <-- 1 digit sign, 10 digits, little-endian
                  // 0 : Ignore if CPU not stopped
                  //     Accept low-order address digit
                  // 1 : Accept remaining address digits
                  // 2 : Calculate word origin in gs RAM
                  //     Validate address
                  //     console_read_gs <= 1;
                  // 3 : Send gs-early digit to out
                  //     digit_ready <= 1;
                  // 4 : digit_ready <= 0;
                  //--------------------------------------------------------------
                  `cmd_read_gs: begin
                     if (ctl_sw_manual) begin
                        busy <= 1;
                        state <= `state_read_gs_1;
                     end
                  end
 
 
                  `cmd_write_gs: begin
                  end
 
                  `cmd_read_acc: begin
                  end
 
                  `cmd_read_dist: begin
                  end
 
                  `cmd_read_prog: begin
                  end
 
                  // 0 : Ignore if not in manual
                  //     Clear gs_ram_addr
                  // 1 : Synchronize with d10
                  //     Turn on console_write_gs
                  // 2 : Put a digit:
                  //     dx: blank
                  //     d0: minus
                  //     d1-d10: zero
                  //     gs_ram_addr++
                  `cmd_clear_gs: begin
                     if (ctl_sw_manual) begin
                        busy <= 1;
                        do_clear_drum <= 1;
                     end
                  end
 
                  `cmd_load_gs: begin
                  end
 
                  `cmd_dump_gs: begin
                  end
 
                  `cmd_power_on_reset: begin
                  end
 
                  `cmd_reset_console: begin
                  end
 
                  `cmd_hard_reset: begin
                     busy <= 1;
                     do_hard_reset <= 1;
                  end
 
               endcase;
            end
 
            // Reset console            
            `state_reset_console_1: begin
               if (d10) state <= `state_reset_console_2;
            end
 
            `state_reset_console_2: begin
               storage_entry_sw[ontime_idx] <= dx? `biq_blank
                                             : d0? `biq_plus : `biq_0;
               addr_sel_sw[ontime_idx[2:3]] <= `biq_0;
               if (d10) state <= `state_idle;
            end
 
            // Program reset key press
            `state_pgm_reset_1: begin
               if (wu & d10) begin
                  man_pgm_reset <= 1;
                  state <= `state_pgm_reset_2;
               end
            end
 
            `state_pgm_reset_2: begin
               if (wu & d10) begin
                  man_pgm_reset <= 0;
                  state <= `state_idle;
               end
            end
 
            // Accumulator reset key press
            `state_acc_reset_1: begin
               if (wu & d10) begin
                  man_acc_reset <= 1;
                  state <= `state_acc_reset_2;
               end
            end
 
            `state_acc_reset_2: begin
               if (wu & d10) begin
                  man_acc_reset <= 0;
                  state <= `state_idle;
               end
            end
 
            // Error reset key press
            `state_err_reset_1: begin
               if (wu & d10) begin
                  err_reset <= 1;
                  state <= `state_err_reset_2;
               end
            end
 
            `state_err_reset_2: begin
               if (wu & d10) begin
                  err_reset <= 0;
                  state <= `state_idle;
               end
            end
 
            // Error sense reset key press
            `state_err_sense_reset_1: begin
               if (wu & d10) begin
                  err_sense_reset <= 1;
                  state <= `state_err_sense_reset_2;
               end
            end
 
            `state_err_sense_reset_2: begin
               if (wu & d10) begin
                  err_sense_reset <= 0;
                  state <= `state_idle;
               end
            end
 
            // Hard reset
            `state_hard_reset_1: begin
               hard_reset <= 0;
               state <= `state_idle;
            end
 
            // Set storage entry switches
            `state_storage_entry_sw_1: begin
               if (d0) begin
                  state <= `state_storage_entry_sw_2;
                  digit_ready <= 1;
                  storage_entry_sw[ontime_idx] <= cmd_digit_in;
               end
            end
 
            `state_storage_entry_sw_2: begin
               storage_entry_sw[ontime_idx] <= cmd_digit_in;
               if (d10) begin
                  state <= `state_idle;
                  digit_ready <= 0;
               end
            end
 
            // Set address selection switches
            `state_addr_sel_sw_1: begin
               if (dx) begin
                  state <= `state_addr_sel_sw_2;
                  digit_ready <= 1;
                  addr_sel_sw[ontime_idx[2:3]] <= cmd_digit_in;
               end
            end
 
            `state_addr_sel_sw_2: begin
               addr_sel_sw[ontime_idx[2:3]] <= cmd_digit_in;
               if (d2) begin
                  state <= `state_idle;
                  digit_ready <= 0;
               end
            end
 
            // Transfer key press
            `state_xfer_key_1: begin
               if (d10) begin
                  console_to_addr <= 1;
                  state <= `state_xfer_key_2;
               end
            end
 
            `state_xfer_key_2: begin
               if (d10) begin
                  console_to_addr <= 0;
                  state <= `state_idle;
               end
            end
 
            // Start key press
            `state_pgm_start_key_1: begin
               if (wu & d10) begin
                  pgm_start <= 1;
                  state <= `state_pgm_start_key_2;
               end
            end
 
            `state_pgm_start_key_2: begin
               if (wu & d10) begin
                  pgm_start <= 0;
                  state <= `state_idle;
               end
            end
 
            // Stop key press
            `state_pgm_stop_key_1: begin
               if (hp) state <= `state_pgm_stop_key_2;
            end
 
            `state_pgm_stop_key_2: begin
               if (hp) begin
                  pgm_stop <= 0;
                  state <= `state_idle;
               end
            end
 
            // Read word from general storage
            //    --> 4 digits address, little-endian
            //    <-- 1 digit sign, 10 digits, little-endian
            // 0 : Ignore if CPU not stopped
            //     Accept low-order address digit
            // 1 : Accept remaining address digits
            // 2 : Calculate word origin in gs RAM
            //     Validate address
            //     console_read_gs <= 1;
            // 3 : Send gs-early digit to out
            //     digit_ready <= 1;
            // 4 : digit_ready <= 0;
            `state_read_gs_1: begin
               if (dx) begin
                  state <= `state_read_gs_2;
                  digit_ready <= 1;
                  gs_addr_u <= cmd_digit_in;
               end
            end
 
            `state_read_gs_2: begin
               if (d0) gs_addr_t <= cmd_digit_in;
               else if (d1) gs_addr_h <= cmd_digit_in;
               else if (d2) begin
                  gs_addr_th <= cmd_digit_in;
                  state <= `state_read_gs_3;
                  digit_ready <= 0;
               end
            end
 
            `state_read_gs_3: begin
               gs_ram_addr <= gs_word_addr;
               state <= `state_read_gs_4;
            end
 
            `state_read_gs_4: begin
               cmd_digit_out <= gs_in;
               state <= `state_read_gs_5;
            end
 
            // 0 : Ignore if not in manual
            //     Clear gs_ram_addr
            // 1 : Synchronize with d10
            //     Turn on console_write_gs
            // 2 : Put a digit:
            //     dx: blank
            //     d0: minus
            //     d1-d10: zero
            //     gs_ram_addr++
            `state_clear_drum_1: begin
               if (d10) begin
                  state <= `state_clear_drum_2;
               end
            end
 
            `state_clear_drum_2: begin
               write_gs <= 1;
               console_out <= dx? `biq_blank
                            : d0? `biq_minus
                            : `biq_0;
               if (write_gs)
                  gs_ram_addr <= gs_ram_addr + 1;
               if (gs_ram_addr == 15'd23999) begin
                  write_gs <= 0;
                  state <= `state_idle;
               end
            end
 
         endcase;
      end
   end;
 
   always @(posedge ap) begin
      if (hard_reset) begin
         data_out <= `biq_blank;
         addr_out <= `biq_blank;
      end else begin
         data_out <= d10? `biq_blank : storage_entry_sw[early_idx];
         addr_out <= (d3 | d4 | d5 | d6)? addr_sel_sw[early_idx[2:3]] : `biq_blank;
      end
   end;
 
   always @(posedge ap) begin
      if (hard_reset) begin
         punch_card       <= 0;
         read_card        <= 0;
         card_digit_ready <= 0;
      end
   end;
 
endmodule

Line No.	Rev	Author	Line
1	7	eightycc	`timescale 1ns / 1ps
2			`//////////////////////////////////////////////////////////////////////////////////`
3			`// IBM 650 Reconstruction in Verilog (i650)`
4			`//`
5			`// This file is part of the IBM 650 Reconstruction in Verilog (i650) project`
6			`// http:////www.opencores.org/project,i650`
7			`//`
8			`// Description: Operator console and external control interface.`
9			`//`
10			`// Additional Comments: See US 2959351, Fig. 75, 76, 76 and 77. Also implements`
11			`// a simple command-based control interface.`
12			`//`
13			`// Copyright (c) 2015 Robert Abeles`
14			`//`
15			`// This source file is free software; you can redistribute it`
16			`// and/or modify it under the terms of the GNU Lesser General`
17			`// Public License as published by the Free Software Foundation;`
18			`// either version 2.1 of the License, or (at your option) any`
19			`// later version.`
20			`//`
21			`// This source is distributed in the hope that it will be`
22			`// useful, but WITHOUT ANY WARRANTY; without even the implied`
23			`// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR`
24			`// PURPOSE. See the GNU Lesser General Public License for more`
25			`// details.`
26			`//`
27			`// You should have received a copy of the GNU Lesser General`
28			`// Public License along with this source; if not, download it`
29			`// from http://www.opencores.org/lgpl.shtml`
30			`//////////////////////////////////////////////////////////////////////////////////`
31			`include "defines.v"
32
33			`module operator_ctl (`
34	11	eightycc	`input rst, clk,`
35	7	eightycc	`input ap, dp,`
36			`input dx, d0, d1, d2, d3, d4, d5, d6, d10,`
37			`input wu, hp,`
38			`input [0:3] early_idx, ontime_idx,`
39
40	11	eightycc	`input [0:6] cmd_digit_in, io_buffer_in, gs_in,`
41	7	eightycc	`input [0:5] command,`
42
43	11	eightycc	`output reg[0:6] data_out, addr_out, console_out,`
44	7	eightycc	`output reg console_to_addr,`
45			`output reg[0:14] gs_ram_addr,`
46	10	eightycc	`output reg read_gs, write_gs,`
47	7	eightycc	`output reg pgm_start, pgm_stop, err_reset, err_sense_reset,`
48			`output run_control, half_or_pgm_stop, ri_storage, ro_storage,`
49			`storage_control,`
50			`output reg man_pgm_reset, man_acc_reset, set_8000, reset_8000,`
51	11	eightycc	`hard_reset,`
52	7	eightycc
53			`output reg[0:6] cmd_digit_out,`
54			`output reg busy, digit_ready,`
55			`output reg punch_card, read_card, card_digit_ready`
56			`);`
57
58			`//-----------------------------------------------------------------------------`
59			`// Operator console switch settings`
60			`//-----------------------------------------------------------------------------`
61			`reg pgm_sw_stop, pgm_sw_run,`
62			`half_cycle_sw_run, half_cycle_sw_half,`
63			`ctl_sw_addr_stop, ctl_sw_run, ctl_sw_manual,`
64			`disp_sw_lacc, disp_sw_uacc, disp_sw_dist, disp_sw_pgm,`
65			`disp_sw_ri, disp_sw_ro,`
66			`ovflw_sw_stop, ovflw_sw_sense, err_sw_stop, err_sw_sense;`
67			`reg [0:6] storage_entry_sw [0:15];`
68			`reg [0:6] addr_sel_sw [0:3];`
69			`assign run_control = disp_sw_lacc \| disp_sw_uacc \| disp_sw_dist \| disp_sw_pgm;`
70			`assign half_or_pgm_stop = half_cycle_sw_half \| pgm_stop;`
71			`assign ri_storage = disp_sw_ri;`
72			`assign ro_storage = disp_sw_ro;`
73			`assign storage_control = run_control \| disp_sw_ro;`
74
75			`reg do_power_on_reset, do_reset_console, do_err_reset, do_err_sense_reset,`
76	11	eightycc	`do_pgm_reset, do_acc_reset, do_hard_reset, do_clear_drum;`
77	7	eightycc	`reg [0:5] state;`
78
79			`reg [0:6] gs_addr_th, gs_addr_h, gs_addr_t, gs_addr_u;`
80	9	eightycc	`wire [0:14] gs_band_addr;`
81	10	eightycc	`wire [0:9] gs_word_offset;`
82	9	eightycc	`ram_band_addr rba(gs_addr_th, gs_addr_h, gs_addr_t, gs_band_addr);`
83	7	eightycc	`ram_word_offset rwo(gs_addr_t, gs_addr_u, gs_word_offset);`
84			`wire [0:14] gs_word_addr = gs_band_addr + gs_word_offset;`
85
86			`define state_idle 6'd0
87
88			`define state_reset_console_1 6'd1
89			`define state_reset_console_2 6'd2
90			`define state_pgm_reset_1 6'd3
91			`define state_pgm_reset_2 6'd4
92			`define state_acc_reset_1 6'd5
93			`define state_acc_reset_2 6'd6
94			`define state_err_reset_1 6'd7
95			`define state_err_reset_2 6'd8
96			`define state_err_sense_reset_1 6'd9
97			`define state_err_sense_reset_2 6'd10
98	11	eightycc	`define state_hard_reset_1 6'd11
99	7	eightycc
100	11	eightycc	`define state_storage_entry_sw_1 6'd12
101			`define state_storage_entry_sw_2 6'd13
102			`define state_addr_sel_sw_1 6'd14
103			`define state_addr_sel_sw_2 6'd15
104	7	eightycc
105	11	eightycc	`define state_xfer_key_1 6'd16
106			`define state_xfer_key_2 6'd17
107			`define state_pgm_start_key_1 6'd18
108			`define state_pgm_start_key_2 6'd19
109			`define state_pgm_stop_key_1 6'd20
110			`define state_pgm_stop_key_2 6'd21
111	7	eightycc
112	11	eightycc	`define state_read_gs_1 6'd30
113			`define state_read_gs_2 6'd31
114			`define state_read_gs_3 6'd32
115			`define state_read_gs_4 6'd33
116			`define state_read_gs_5 6'd34
117	7	eightycc
118	11	eightycc	`define state_clear_drum_1 6'd50
119			`define state_clear_drum_2 6'd51
120			`define state_clear_drum_3 6'd52
121
122	7	eightycc	`//-----------------------------------------------------------------------------`
123			`// Operator console state machine`
124			`//-----------------------------------------------------------------------------`
125	11	eightycc	`always @(posedge clk) begin`
126	7	eightycc	`if (rst) begin`
127			`console_to_addr <= 0;`
128			`pgm_start <= 0;`
129			`pgm_stop <= 0;`
130			`err_reset <= 0;`
131			`err_sense_reset <= 0;`
132			`man_pgm_reset <= 0;`
133			`man_acc_reset <= 0;`
134			`set_8000 <= 0;`
135			`reset_8000 <= 0;`
136	11	eightycc	`hard_reset <= 0;`
137	7	eightycc
138			`// reset console switches`
139			`pgm_sw_stop <= 0;`
140			`pgm_sw_run <= 1;`
141	11	eightycc	`half_cycle_sw_run <= 1;`
142			`half_cycle_sw_half <= 0;`
143	7	eightycc	`ctl_sw_addr_stop <= 0;`
144			`ctl_sw_run <= 1;`
145			`ctl_sw_manual <= 0;`
146			`disp_sw_lacc <= 0;`
147			`disp_sw_uacc <= 0;`
148			`disp_sw_dist <= 1;`
149			`disp_sw_pgm <= 0;`
150			`disp_sw_ri <= 0;`
151			`disp_sw_ro <= 0;`
152			`ovflw_sw_stop <= 1;`
153			`ovflw_sw_sense <= 0;`
154			`err_sw_stop <= 1;`
155			`err_sw_sense <= 0;`
156
157			state <= `state_idle;
158			`busy <= 1;`
159			`digit_ready <= 0;`
160			cmd_digit_out <= `biq_blank;
161
162			`do_power_on_reset <= 1;`
163			`do_reset_console <= 0;`
164			`do_err_reset <= 0;`
165			`do_err_sense_reset <= 0;`
166			`do_pgm_reset <= 0;`
167			`do_acc_reset <= 0;`
168	11	eightycc	`do_hard_reset <= 0;`
169			`do_clear_drum <= 0;`
170	7	eightycc
171			`gs_ram_addr <= 15'd0;`
172	9	eightycc	`read_gs <= 0;`
173	10	eightycc	`write_gs <= 0;`
174	11	eightycc	console_out <= `biq_blank;
175			`end else if (dp) begin`
176	7	eightycc	`case (state)`
177			`state_idle: begin
178			`case (command)`
179			`cmd_none: begin
180			`if (do_power_on_reset) begin`
181			`do_power_on_reset <= 0;`
182			`do_reset_console <= 1;`
183			`do_pgm_reset <= 1;`
184			`do_acc_reset <= 1;`
185			`do_err_reset <= 1;`
186			`do_err_sense_reset <= 1;`
187	11	eightycc	`do_hard_reset <= 1;`
188			`do_clear_drum <= 1;`
189			`end else if (do_hard_reset) begin`
190			`do_hard_reset <= 0;`
191			`hard_reset <= 1;`
192			state <= `state_hard_reset_1;
193	7	eightycc	`end else if (do_reset_console) begin`
194			`do_reset_console <= 0;`
195			state <= `state_reset_console_1;
196	11	eightycc	`end else if (do_clear_drum) begin`
197			`do_clear_drum <= 0;`
198			`gs_ram_addr <= 15'd0;`
199			state <= `state_clear_drum_1;
200	7	eightycc	`end else if (do_pgm_reset) begin`
201			`do_pgm_reset <= 0;`
202			state <= `state_pgm_reset_1;
203			`end else if (do_acc_reset) begin`
204			`do_acc_reset <= 0;`
205			`man_acc_reset <= 1;`
206			state <= `state_acc_reset_1;
207			`end else if (do_err_reset) begin`
208			`do_err_reset <= 0;`
209			`err_reset <= 1;`
210			state <= `state_err_reset_1;
211			`end else if (do_err_sense_reset) begin`
212			`do_err_sense_reset <= 0;`
213			`err_sense_reset <= 1;`
214			state <= `state_err_sense_reset_1;
215			`end else begin`
216			`busy <= 0;`
217			`digit_ready <= 0;`
218			`end`
219			`end`
220
221			`cmd_pgm_sw_stop: begin
222			`busy <= 1;`
223			`pgm_sw_stop <= 1;`
224			`pgm_sw_run <= 0;`
225			`end`
226
227			`cmd_pgm_sw_run: begin
228			`busy <= 1;`
229			`pgm_sw_stop <= 0;`
230			`pgm_sw_run <= 1;`
231			`end`
232
233			`cmd_half_cycle_sw_run: begin
234			`busy <= 1;`
235			`half_cycle_sw_run <= 1;`
236			`half_cycle_sw_half <= 0;`
237			`end`
238
239			`cmd_half_cycle_sw_half: begin
240			`busy <= 1;`
241			`half_cycle_sw_run <= 0;`
242			`half_cycle_sw_half <= 1;`
243			`end`
244
245			`cmd_ctl_sw_addr_stop: begin
246			`busy <= 1;`
247			`ctl_sw_addr_stop <= 1;`
248			`ctl_sw_run <= 0;`
249			`ctl_sw_manual <= 0;`
250			`end`
251
252			`cmd_ctl_sw_run: begin
253			`busy <= 1;`
254			`ctl_sw_addr_stop <= 0;`
255			`ctl_sw_run <= 1;`
256			`ctl_sw_manual <= 0;`
257			`end`
258
259			`cmd_ctl_sw_manual: begin
260			`busy <= 1;`
261			`ctl_sw_addr_stop <= 0;`
262			`ctl_sw_run <= 0;`
263			`ctl_sw_manual <= 1;`
264			`end`
265
266			`cmd_disp_sw_lacc: begin
267			`busy <= 1;`
268			`disp_sw_lacc <= 1;`
269			`disp_sw_uacc <= 0;`
270			`disp_sw_dist <= 0;`
271			`disp_sw_pgm <= 0;`
272			`disp_sw_ri <= 0;`
273			`disp_sw_ro <= 0;`
274			`end`
275
276			`cmd_disp_sw_uacc: begin
277			`busy <= 1;`
278			`disp_sw_lacc <= 0;`
279			`disp_sw_uacc <= 1;`
280			`disp_sw_dist <= 0;`
281			`disp_sw_pgm <= 0;`
282			`disp_sw_ri <= 0;`
283			`disp_sw_ro <= 0;`
284			`end`
285
286			`cmd_disp_sw_dist: begin
287			`busy <= 1;`
288			`disp_sw_lacc <= 0;`
289			`disp_sw_uacc <= 0;`
290			`disp_sw_dist <= 1;`
291			`disp_sw_pgm <= 0;`
292			`disp_sw_ri <= 0;`
293			`disp_sw_ro <= 0;`
294			`end`
295
296			`cmd_disp_sw_prog: begin
297			`busy <= 1;`
298			`disp_sw_lacc <= 0;`
299			`disp_sw_uacc <= 0;`
300			`disp_sw_dist <= 0;`
301			`disp_sw_pgm <= 1;`
302			`disp_sw_ri <= 0;`
303			`disp_sw_ro <= 0;`
304			`end`
305
306			`cmd_disp_sw_ri: begin
307			`busy <= 1;`
308			`disp_sw_lacc <= 0;`
309			`disp_sw_uacc <= 0;`
310			`disp_sw_dist <= 0;`
311			`disp_sw_pgm <= 0;`
312			`disp_sw_ri <= 1;`
313			`disp_sw_ro <= 0;`
314			`end`
315
316			`cmd_disp_sw_ro: begin
317			`busy <= 1;`
318			`disp_sw_lacc <= 0;`
319			`disp_sw_uacc <= 0;`
320			`disp_sw_dist <= 0;`
321			`disp_sw_pgm <= 0;`
322			`disp_sw_ri <= 0;`
323			`disp_sw_ro <= 1;`
324			`end`
325
326			`cmd_ovflw_sw_stop: begin
327			`busy <= 1;`
328			`ovflw_sw_stop <= 1;`
329			`ovflw_sw_sense <= 0;`
330			`end`
331
332			`cmd_ovflw_sw_sense: begin
333			`busy <= 1;`
334			`ovflw_sw_stop <= 0;`
335			`ovflw_sw_sense <= 1;`
336			`end`
337
338			`cmd_err_sw_stop: begin
339			`busy <= 1;`
340			`err_sw_stop <= 1;`
341			`err_sw_sense <= 0;`
342			`end`
343
344			`cmd_err_sw_sense: begin
345			`busy <= 1;`
346			`err_sw_stop <= 0;`
347			`err_sw_sense <= 1;`
348			`end`
349
350			`cmd_storage_entry_sw: begin
351			`busy <= 1;`
352			state <= `state_storage_entry_sw_1;
353			`end`
354
355			`cmd_addr_sel_sw: begin
356			`busy <= 1;`
357			state <= `state_addr_sel_sw_1;
358			`end`
359
360			`cmd_xfer_key: begin
361			`if (ctl_sw_manual) begin`
362			`busy <= 1;`
363			state <= `state_xfer_key_1;
364			`end`
365			`end`
366
367			`cmd_pgm_start_key: begin
368			`busy <= 1;`
369			state <= `state_pgm_start_key_1;
370			`end`
371
372			`cmd_pgm_stop_key: begin
373			`busy <= 1;`
374			`pgm_stop <= 1;`
375			state <= `state_pgm_stop_key_1;
376			`end`
377
378			`cmd_pgm_reset_key: begin
379	11	eightycc	`busy <= 1;`
380	7	eightycc	`do_pgm_reset <= 1;`
381			`do_err_reset <= 1;`
382			`end`
383
384			`cmd_comp_reset_key: begin
385	11	eightycc	`busy <= 1;`
386	7	eightycc	`do_pgm_reset <= 1;`
387			`do_acc_reset <= 1;`
388			`do_err_reset <= 1;`
389			`end`
390
391			`cmd_acc_reset_key: begin
392	11	eightycc	`busy <= 1;`
393	7	eightycc	`do_acc_reset <= 1;`
394			`do_err_reset <= 1;`
395			`end`
396
397			`cmd_err_reset_key: begin
398	11	eightycc	`busy <= 1;`
399	7	eightycc	`do_err_reset <= 1;`
400			`end`
401
402			`cmd_err_sense_reset_key: begin
403	11	eightycc	`busy <= 1;`
404	7	eightycc	`do_err_sense_reset <= 1;`
405			`end`
406
407			`//--------------------------------------------------------------`
408			`// Read from general storage:`
409			`// --> 4 digits address, little-endian`
410			`// <-- 1 digit sign, 10 digits, little-endian`
411			`// 0 : Ignore if CPU not stopped`
412			`// Accept low-order address digit`
413			`// 1 : Accept remaining address digits`
414			`// 2 : Calculate word origin in gs RAM`
415			`// Validate address`
416			`// console_read_gs <= 1;`
417			`// 3 : Send gs-early digit to out`
418			`// digit_ready <= 1;`
419			`// 4 : digit_ready <= 0;`
420			`//--------------------------------------------------------------`
421			`cmd_read_gs: begin
422			`if (ctl_sw_manual) begin`
423			`busy <= 1;`
424			state <= `state_read_gs_1;
425			`end`
426			`end`
427	10	eightycc
428	9	eightycc
429			`cmd_write_gs: begin
430	10	eightycc	`end`
431
432	9	eightycc	`cmd_read_acc: begin
433	10	eightycc	`end`
434
435	9	eightycc	`cmd_read_dist: begin
436	10	eightycc	`end`
437
438	9	eightycc	`cmd_read_prog: begin
439	10	eightycc	`end`
440
441			`// 0 : Ignore if not in manual`
442			`// Clear gs_ram_addr`
443			`// 1 : Synchronize with d10`
444			`// Turn on console_write_gs`
445			`// 2 : Put a digit:`
446			`// dx: blank`
447			`// d0: minus`
448			`// d1-d10: zero`
449			`// gs_ram_addr++`
450	9	eightycc	`cmd_clear_gs: begin
451	11	eightycc	`if (ctl_sw_manual) begin`
452			`busy <= 1;`
453			`do_clear_drum <= 1;`
454			`end`
455	10	eightycc	`end`
456
457	9	eightycc	`cmd_load_gs: begin
458	10	eightycc	`end`
459
460	9	eightycc	`cmd_dump_gs: begin
461	10	eightycc	`end`
462
463	9	eightycc	`cmd_power_on_reset: begin
464	10	eightycc	`end`
465
466	9	eightycc	`cmd_reset_console: begin
467	10	eightycc	`end`
468	7	eightycc
469	11	eightycc	`cmd_hard_reset: begin
470			`busy <= 1;`
471			`do_hard_reset <= 1;`
472			`end`
473
474	7	eightycc	`endcase;`
475			`end`
476
477			`// Reset console`
478			`state_reset_console_1: begin
479			if (d10) state <= `state_reset_console_2;
480			`end`
481
482			`state_reset_console_2: begin
483	11	eightycc	storage_entry_sw[ontime_idx] <= dx? `biq_blank
484			: d0? `biq_plus : `biq_0;
485	7	eightycc	addr_sel_sw[ontime_idx[2:3]] <= `biq_0;
486			if (d10) state <= `state_idle;
487			`end`
488
489			`// Program reset key press`
490			`state_pgm_reset_1: begin
491			`if (wu & d10) begin`
492			`man_pgm_reset <= 1;`
493			state <= `state_pgm_reset_2;
494			`end`
495			`end`
496
497			`state_pgm_reset_2: begin
498			`if (wu & d10) begin`
499			`man_pgm_reset <= 0;`
500			state <= `state_idle;

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