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[/] [i650/] [trunk/] [rtl/] [operator_ctl.v] - Blame information for rev 7

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// IBM 650 Reconstruction in Verilog (i650)
// 
// This file is part of the IBM 650 Reconstruction in Verilog (i650) project
// http:////www.opencores.org/project,i650
//
// Description: Operator console and external control interface.
// 
// Additional Comments: See US 2959351, Fig. 75, 76, 76 and 77. Also implements
//  a simple command-based control interface.
//
// Copyright (c) 2015 Robert Abeles
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE.  See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, download it
// from http://www.opencores.org/lgpl.shtml
//////////////////////////////////////////////////////////////////////////////////
`include "defines.v"
 
module operator_ctl (
      input rst,
      input ap, dp,
      input dx, d0, d1, d2, d3, d4, d5, d6, d10,
      input wu, hp,
      input [0:3] early_idx, ontime_idx,
 
      input [0:6] cmd_digit_in, io_buffer_in,
      input [0:5] command,
 
      output reg[0:6] data_out, addr_out,
      output reg console_to_addr,
      output reg[0:14] gs_ram_addr,
      output reg pgm_start, pgm_stop, err_reset, err_sense_reset,
      output run_control, half_or_pgm_stop, ri_storage, ro_storage,
             storage_control,
      output reg man_pgm_reset, man_acc_reset, set_8000, reset_8000,
 
      output reg[0:6] cmd_digit_out,
      output reg busy, digit_ready,
      output reg punch_card, read_card, card_digit_ready
   );
 
   //-----------------------------------------------------------------------------
   // Operator console switch settings
   //-----------------------------------------------------------------------------
   reg pgm_sw_stop, pgm_sw_run,
       half_cycle_sw_run, half_cycle_sw_half,
       ctl_sw_addr_stop, ctl_sw_run, ctl_sw_manual,
       disp_sw_lacc, disp_sw_uacc, disp_sw_dist, disp_sw_pgm,
       disp_sw_ri, disp_sw_ro,
       ovflw_sw_stop, ovflw_sw_sense, err_sw_stop, err_sw_sense;
   reg [0:6] storage_entry_sw [0:15];
   reg [0:6] addr_sel_sw [0:3];
   assign run_control = disp_sw_lacc | disp_sw_uacc | disp_sw_dist | disp_sw_pgm;
   assign half_or_pgm_stop = half_cycle_sw_half | pgm_stop;
   assign ri_storage = disp_sw_ri;
   assign ro_storage = disp_sw_ro;
   assign storage_control = run_control | disp_sw_ro;
 
   reg do_power_on_reset, do_reset_console, do_err_reset, do_err_sense_reset,
       do_pgm_reset, do_acc_reset;
   reg [0:5] state;
 
   reg [0:6] gs_addr_th, gs_addr_h, gs_addr_t, gs_addr_u;
   wire [0:14] gs_band_addr, gs_word_offset;
   ram_band_addr rba(gs_addr_th[`biq_q1], gs_addr_h, gs_addr_t[`biq_b5],
                     gs_band_addr);
   ram_word_offset rwo(gs_addr_t, gs_addr_u, gs_word_offset);
   wire [0:14] gs_word_addr = gs_band_addr + gs_word_offset;
 
   `define state_idle                  6'd0
 
   `define state_reset_console_1       6'd1
   `define state_reset_console_2       6'd2
   `define state_pgm_reset_1           6'd3
   `define state_pgm_reset_2           6'd4
   `define state_acc_reset_1           6'd5
   `define state_acc_reset_2           6'd6
   `define state_err_reset_1           6'd7
   `define state_err_reset_2           6'd8
   `define state_err_sense_reset_1     6'd9
   `define state_err_sense_reset_2     6'd10
 
   `define state_storage_entry_sw_1    6'd11
   `define state_storage_entry_sw_2    6'd12
   `define state_addr_sel_sw_1         6'd13
   `define state_addr_sel_sw_2         6'd14
 
   `define state_xfer_key_1            6'd15
   `define state_xfer_key_2            6'd16
   `define state_pgm_start_key_1       6'd17
   `define state_pgm_start_key_2       6'd18
   `define state_pgm_stop_key_1        6'd19
   `define state_pgm_stop_key_2        6'd20
 
   `define state_read_gs_1             6'd31
   `define state_read_gs_2             6'd32
   `define state_read_gs_3             6'd33
   `define state_read_gs_4             6'd34
 
   //-----------------------------------------------------------------------------
   // Operator console state machine
   //-----------------------------------------------------------------------------
   always @(posedge rst, posedge dp) begin
      if (rst) begin
         console_to_addr  <= 0;
         pgm_start        <= 0;
         pgm_stop         <= 0;
         err_reset        <= 0;
         err_sense_reset  <= 0;
         man_pgm_reset    <= 0;
         man_acc_reset    <= 0;
         set_8000         <= 0;
         reset_8000       <= 0;
 
         // reset console switches
         pgm_sw_stop      <= 0;
         pgm_sw_run       <= 1;
         ctl_sw_addr_stop <= 0;
         ctl_sw_run       <= 1;
         ctl_sw_manual    <= 0;
         disp_sw_lacc     <= 0;
         disp_sw_uacc     <= 0;
         disp_sw_dist     <= 1;
         disp_sw_pgm     <= 0;
         disp_sw_ri       <= 0;
         disp_sw_ro       <= 0;
         ovflw_sw_stop    <= 1;
         ovflw_sw_sense   <= 0;
         err_sw_stop      <= 1;
         err_sw_sense     <= 0;
 
         state         <= `state_idle;
         busy          <= 1;
         digit_ready   <= 0;
         cmd_digit_out <= `biq_blank;
 
         do_power_on_reset  <= 1;
         do_reset_console   <= 0;
         do_err_reset       <= 0;
         do_err_sense_reset <= 0;
         do_pgm_reset       <= 0;
         do_acc_reset       <= 0;
 
         gs_ram_addr        <= 15'd0;
 
      end else begin
         case (state)
            `state_idle: begin
               case (command)
                  `cmd_none: begin
                     if (do_power_on_reset) begin
                        do_power_on_reset  <= 0;
                        do_reset_console   <= 1;
                        do_pgm_reset       <= 1;
                        do_acc_reset       <= 1;
                        do_err_reset       <= 1;
                        do_err_sense_reset <= 1;
                     end else if (do_reset_console) begin
                        do_reset_console   <= 0;
                        state <= `state_reset_console_1;
                     end else if (do_pgm_reset) begin
                        do_pgm_reset       <= 0;
                        state <= `state_pgm_reset_1;
                     end else if (do_acc_reset) begin
                        do_acc_reset       <= 0;
                        man_acc_reset      <= 1;
                        state <= `state_acc_reset_1;
                     end else if (do_err_reset) begin
                        do_err_reset       <= 0;
                        err_reset          <= 1;
                        state <= `state_err_reset_1;
                     end else if (do_err_sense_reset) begin
                        do_err_sense_reset <= 0;
                        err_sense_reset <= 1;
                        state <= `state_err_sense_reset_1;
                     end else begin
                        busy <= 0;
                        digit_ready <= 0;
                     end
                  end
 
                  `cmd_pgm_sw_stop: begin
                     busy <= 1;
                     pgm_sw_stop <= 1;
                     pgm_sw_run  <= 0;
                  end
 
                  `cmd_pgm_sw_run: begin
                     busy <= 1;
                     pgm_sw_stop <= 0;
                     pgm_sw_run  <= 1;
                  end
 
                  `cmd_half_cycle_sw_run: begin
                     busy <= 1;
                     half_cycle_sw_run  <= 1;
                     half_cycle_sw_half <= 0;
                  end
 
                  `cmd_half_cycle_sw_half: begin
                     busy <= 1;
                     half_cycle_sw_run  <= 0;
                     half_cycle_sw_half <= 1;
                  end
 
                  `cmd_ctl_sw_addr_stop: begin
                     busy <= 1;
                     ctl_sw_addr_stop <= 1;
                     ctl_sw_run       <= 0;
                     ctl_sw_manual    <= 0;
                  end
 
                  `cmd_ctl_sw_run: begin
                     busy <= 1;
                     ctl_sw_addr_stop <= 0;
                     ctl_sw_run       <= 1;
                     ctl_sw_manual    <= 0;
                  end
 
                  `cmd_ctl_sw_manual: begin
                     busy <= 1;
                     ctl_sw_addr_stop <= 0;
                     ctl_sw_run       <= 0;
                     ctl_sw_manual    <= 1;
                  end
 
                  `cmd_disp_sw_lacc: begin
                     busy <= 1;
                     disp_sw_lacc <= 1;
                     disp_sw_uacc <= 0;
                     disp_sw_dist <= 0;
                     disp_sw_pgm <= 0;
                     disp_sw_ri   <= 0;
                     disp_sw_ro   <= 0;
                  end
 
                  `cmd_disp_sw_uacc: begin
                     busy <= 1;
                     disp_sw_lacc <= 0;
                     disp_sw_uacc <= 1;
                     disp_sw_dist <= 0;
                     disp_sw_pgm <= 0;
                     disp_sw_ri   <= 0;
                     disp_sw_ro   <= 0;
                  end
 
                  `cmd_disp_sw_dist: begin
                     busy <= 1;
                     disp_sw_lacc <= 0;
                     disp_sw_uacc <= 0;
                     disp_sw_dist <= 1;
                     disp_sw_pgm <= 0;
                     disp_sw_ri   <= 0;
                     disp_sw_ro   <= 0;
                  end
 
                  `cmd_disp_sw_prog: begin
                     busy <= 1;
                     disp_sw_lacc <= 0;
                     disp_sw_uacc <= 0;
                     disp_sw_dist <= 0;
                     disp_sw_pgm <= 1;
                     disp_sw_ri   <= 0;
                     disp_sw_ro   <= 0;
                  end
 
                  `cmd_disp_sw_ri: begin
                     busy <= 1;
                     disp_sw_lacc <= 0;
                     disp_sw_uacc <= 0;
                     disp_sw_dist <= 0;
                     disp_sw_pgm <= 0;
                     disp_sw_ri   <= 1;
                     disp_sw_ro   <= 0;
                  end
 
                  `cmd_disp_sw_ro: begin
                     busy <= 1;
                     disp_sw_lacc <= 0;
                     disp_sw_uacc <= 0;
                     disp_sw_dist <= 0;
                     disp_sw_pgm <= 0;
                     disp_sw_ri   <= 0;
                     disp_sw_ro   <= 1;
                  end
 
                  `cmd_ovflw_sw_stop: begin
                     busy <= 1;
                     ovflw_sw_stop  <= 1;
                     ovflw_sw_sense <= 0;
                  end
 
                  `cmd_ovflw_sw_sense: begin
                     busy <= 1;
                     ovflw_sw_stop  <= 0;
                     ovflw_sw_sense <= 1;
                  end
 
                  `cmd_err_sw_stop: begin
                     busy <= 1;
                     err_sw_stop  <= 1;
                     err_sw_sense <= 0;
                  end
 
                  `cmd_err_sw_sense: begin
                     busy <= 1;
                     err_sw_stop  <= 0;
                     err_sw_sense <= 1;
                  end
 
                  `cmd_storage_entry_sw: begin
                     busy <= 1;
                     state <= `state_storage_entry_sw_1;
                  end
 
                  `cmd_addr_sel_sw: begin
                     busy <= 1;
                     state <= `state_addr_sel_sw_1;
                  end
 
                  `cmd_xfer_key: begin
                     if (ctl_sw_manual) begin
                        busy <= 1;
                        state <= `state_xfer_key_1;
                     end
                  end
 
                  `cmd_pgm_start_key: begin
                     busy <= 1;
                     state <= `state_pgm_start_key_1;
                  end
 
                  `cmd_pgm_stop_key: begin
                     busy <= 1;
                     pgm_stop <= 1;
                     state <= `state_pgm_stop_key_1;
                  end
 
                  `cmd_pgm_reset_key: begin
                     do_pgm_reset <= 1;
                     do_err_reset <= 1;
                  end
 
                  `cmd_comp_reset_key: begin
                     do_pgm_reset <= 1;
                     do_acc_reset <= 1;
                     do_err_reset <= 1;
                  end
 
                  `cmd_acc_reset_key: begin
                     do_acc_reset <= 1;
                     do_err_reset <= 1;
                  end
 
                  `cmd_err_reset_key: begin
                     do_err_reset <= 1;
                  end
 
                  `cmd_err_sense_reset_key: begin
                     do_err_sense_reset <= 1;
                  end
 
                  //--------------------------------------------------------------
                  // Read from general storage:
                  //    --> 4 digits address, little-endian
                  //    <-- 1 digit sign, 10 digits, little-endian
                  // 0 : Ignore if CPU not stopped
                  //     Accept low-order address digit
                  // 1 : Accept remaining address digits
                  // 2 : Calculate word origin in gs RAM
                  //     Validate address
                  //     console_read_gs <= 1;
                  // 3 : Send gs-early digit to out
                  //     digit_ready <= 1;
                  // 4 : digit_ready <= 0;
                  //--------------------------------------------------------------
                  `cmd_read_gs: begin
                     if (ctl_sw_manual) begin
                        busy <= 1;
                        state <= `state_read_gs_1;
                     end
                  end
 `ifdef 0
                  `cmd_write_gs:
                  `cmd_read_acc:
                  `cmd_read_dist:
                  `cmd_read_prog:
                  `cmd_clear_gs:
                  `cmd_load_gs:
                  `cmd_dump_gs:
                  `cmd_power_on_reset:
                  `cmd_reset_console:
 `endif
 
               endcase;
            end
 
            // Reset console            
            `state_reset_console_1: begin
               if (d10) state <= `state_reset_console_2;
            end
 
            `state_reset_console_2: begin
               storage_entry_sw[ontime_idx] <= d0? `biq_plus : `biq_0;
               addr_sel_sw[ontime_idx[2:3]] <= `biq_0;
               if (d10) state <= `state_idle;
            end
 
            // Program reset key press
            `state_pgm_reset_1: begin
               if (wu & d10) begin
                  man_pgm_reset <= 1;
                  state <= `state_pgm_reset_2;
               end
            end
 
            `state_pgm_reset_2: begin
               if (wu & d10) begin
                  man_pgm_reset <= 0;
                  state <= `state_idle;
               end
            end
 
            // Accumulator reset key press
            `state_acc_reset_1: begin
               if (wu & d10) begin
                  man_acc_reset <= 1;
                  state <= `state_acc_reset_2;
               end
            end
 
            `state_acc_reset_2: begin
               if (wu & d10) begin
                  man_acc_reset <= 0;
                  state <= `state_idle;
               end
            end
 
            // Error reset key press
            `state_err_reset_1: begin
               if (wu & d10) begin
                  err_reset <= 1;
                  state <= `state_err_reset_2;
               end
            end
 
            `state_err_reset_2: begin
               if (wu & d10) begin
                  err_reset <= 0;
                  state <= `state_idle;
               end
            end
 
            // Error sense reset key press
            `state_err_sense_reset_1: begin
               if (wu & d10) begin
                  err_sense_reset <= 1;
                  state <= `state_err_sense_reset_2;
               end
            end
 
            `state_err_sense_reset_2: begin
               if (wu & d10) begin
                  err_sense_reset <= 0;
                  state <= `state_idle;
               end
            end
 
            // Set storage entry switches
            `state_storage_entry_sw_1: begin
               if (d0) begin
                  state <= `state_storage_entry_sw_2;
                  digit_ready <= 1;
                  storage_entry_sw[ontime_idx] <= cmd_digit_in;
               end
            end
 
            `state_storage_entry_sw_2: begin
               storage_entry_sw[ontime_idx] <= cmd_digit_in;
               if (d10) begin
                  state <= `state_idle;
                  digit_ready <= 0;
               end
            end
 
            // Set address selection switches
            `state_addr_sel_sw_1: begin
               if (dx) begin
                  state <= `state_addr_sel_sw_2;
                  digit_ready <= 1;
                  addr_sel_sw[ontime_idx[2:3]] <= cmd_digit_in;
               end
            end
 
            `state_addr_sel_sw_2: begin
               addr_sel_sw[ontime_idx[2:3]] <= cmd_digit_in;
               if (d2) begin
                  state <= `state_idle;
                  digit_ready <= 0;
               end
            end
 
            // Transfer key press
            `state_xfer_key_1: begin
               if (d10) begin
                  console_to_addr <= 1;
                  state <= `state_xfer_key_2;
               end
            end
 
            `state_xfer_key_2: begin
               if (d10) begin
                  console_to_addr <= 0;
                  state <= `state_idle;
               end
            end
 
            // Start key press
            `state_pgm_start_key_1: begin
               if (wu & d10) begin
                  pgm_start <= 1;
                  state <= `state_pgm_start_key_2;
               end
            end
 
            `state_pgm_start_key_2: begin
               if (wu & d10) begin
                  pgm_start <= 0;
                  state <= `state_idle;
               end
            end
 
            // Stop key press
            `state_pgm_stop_key_1: begin
               if (hp) state <= `state_pgm_stop_key_2;
            end
 
            `state_pgm_stop_key_2: begin
               if (hp) begin
                  pgm_stop <= 0;
                  state <= `state_idle;
               end
            end
 
            // Read word from general storage
            //    --> 4 digits address, little-endian
            //    <-- 1 digit sign, 10 digits, little-endian
            // 0 : Ignore if CPU not stopped
            //     Accept low-order address digit
            // 1 : Accept remaining address digits
            // 2 : Calculate word origin in gs RAM
            //     Validate address
            //     console_read_gs <= 1;
            // 3 : Send gs-early digit to out
            //     digit_ready <= 1;
            // 4 : digit_ready <= 0;
            `state_read_gs_1: begin
               if (dx) begin
                  state <= `state_read_gs_2;
                  digit_ready <= 1;
                  gs_addr_u <= cmd_digit_in;
               end
            end
 
            `state_read_gs_2: begin
               if (d0) gs_addr_t <= cmd_digit_in;
               else if (d1) gs_addr_h <= cmd_digit_in;
               else if (d2) begin
                  gs_addr_th <= cmd_digit_in;
                  state <= `state_read_gs_3;
                  digit_ready <= 0;
               end
            end
 
            `state_read_gs_3: begin
               gs_ram_addr <= gs_word_addr;
               state <= `state_read_gs_4;
            end
 
         endcase;
      end
   end;
 
   always @(posedge rst, posedge ap) begin
      if (rst) begin
         data_out <= `biq_blank;
         addr_out <= `biq_blank;
      end else begin
         data_out <= d10? `biq_blank : storage_entry_sw[early_idx];
         addr_out <= (d3 | d4 | d5 | d6)? addr_sel_sw[early_idx[2:3]] : `biq_blank;
      end
   end;
 
   always @(posedge rst, posedge ap) begin
      if (rst) begin
         punch_card       <= 0;
         read_card        <= 0;
         card_digit_ready <= 0;
      end
   end;
 
endmodule

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[/] [i650/] [trunk/] [rtl/] [operator_ctl.v] - Blame information for rev 7

Line No.	Rev	Author	Line
1	7	eightycc	`timescale 1ns / 1ps
2			`//////////////////////////////////////////////////////////////////////////////////`
3			`// IBM 650 Reconstruction in Verilog (i650)`
4			`//`
5			`// This file is part of the IBM 650 Reconstruction in Verilog (i650) project`
6			`// http:////www.opencores.org/project,i650`
7			`//`
8			`// Description: Operator console and external control interface.`
9			`//`
10			`// Additional Comments: See US 2959351, Fig. 75, 76, 76 and 77. Also implements`
11			`// a simple command-based control interface.`
12			`//`
13			`// Copyright (c) 2015 Robert Abeles`
14			`//`
15			`// This source file is free software; you can redistribute it`
16			`// and/or modify it under the terms of the GNU Lesser General`
17			`// Public License as published by the Free Software Foundation;`
18			`// either version 2.1 of the License, or (at your option) any`
19			`// later version.`
20			`//`
21			`// This source is distributed in the hope that it will be`
22			`// useful, but WITHOUT ANY WARRANTY; without even the implied`
23			`// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR`
24			`// PURPOSE. See the GNU Lesser General Public License for more`
25			`// details.`
26			`//`
27			`// You should have received a copy of the GNU Lesser General`
28			`// Public License along with this source; if not, download it`
29			`// from http://www.opencores.org/lgpl.shtml`
30			`//////////////////////////////////////////////////////////////////////////////////`
31			`include "defines.v"
32
33			`module operator_ctl (`
34			`input rst,`
35			`input ap, dp,`
36			`input dx, d0, d1, d2, d3, d4, d5, d6, d10,`
37			`input wu, hp,`
38			`input [0:3] early_idx, ontime_idx,`
39
40			`input [0:6] cmd_digit_in, io_buffer_in,`
41			`input [0:5] command,`
42
43			`output reg[0:6] data_out, addr_out,`
44			`output reg console_to_addr,`
45			`output reg[0:14] gs_ram_addr,`
46			`output reg pgm_start, pgm_stop, err_reset, err_sense_reset,`
47			`output run_control, half_or_pgm_stop, ri_storage, ro_storage,`
48			`storage_control,`
49			`output reg man_pgm_reset, man_acc_reset, set_8000, reset_8000,`
50
51			`output reg[0:6] cmd_digit_out,`
52			`output reg busy, digit_ready,`
53			`output reg punch_card, read_card, card_digit_ready`
54			`);`
55
56			`//-----------------------------------------------------------------------------`
57			`// Operator console switch settings`
58			`//-----------------------------------------------------------------------------`
59			`reg pgm_sw_stop, pgm_sw_run,`
60			`half_cycle_sw_run, half_cycle_sw_half,`
61			`ctl_sw_addr_stop, ctl_sw_run, ctl_sw_manual,`
62			`disp_sw_lacc, disp_sw_uacc, disp_sw_dist, disp_sw_pgm,`
63			`disp_sw_ri, disp_sw_ro,`
64			`ovflw_sw_stop, ovflw_sw_sense, err_sw_stop, err_sw_sense;`
65			`reg [0:6] storage_entry_sw [0:15];`
66			`reg [0:6] addr_sel_sw [0:3];`
67			`assign run_control = disp_sw_lacc \| disp_sw_uacc \| disp_sw_dist \| disp_sw_pgm;`
68			`assign half_or_pgm_stop = half_cycle_sw_half \| pgm_stop;`
69			`assign ri_storage = disp_sw_ri;`
70			`assign ro_storage = disp_sw_ro;`
71			`assign storage_control = run_control \| disp_sw_ro;`
72
73			`reg do_power_on_reset, do_reset_console, do_err_reset, do_err_sense_reset,`
74			`do_pgm_reset, do_acc_reset;`
75			`reg [0:5] state;`
76
77			`reg [0:6] gs_addr_th, gs_addr_h, gs_addr_t, gs_addr_u;`
78			`wire [0:14] gs_band_addr, gs_word_offset;`
79			ram_band_addr rba(gs_addr_th[`biq_q1], gs_addr_h, gs_addr_t[`biq_b5],
80			`gs_band_addr);`
81			`ram_word_offset rwo(gs_addr_t, gs_addr_u, gs_word_offset);`
82			`wire [0:14] gs_word_addr = gs_band_addr + gs_word_offset;`
83
84			`define state_idle 6'd0
85
86			`define state_reset_console_1 6'd1
87			`define state_reset_console_2 6'd2
88			`define state_pgm_reset_1 6'd3
89			`define state_pgm_reset_2 6'd4
90			`define state_acc_reset_1 6'd5
91			`define state_acc_reset_2 6'd6
92			`define state_err_reset_1 6'd7
93			`define state_err_reset_2 6'd8
94			`define state_err_sense_reset_1 6'd9
95			`define state_err_sense_reset_2 6'd10
96
97			`define state_storage_entry_sw_1 6'd11
98			`define state_storage_entry_sw_2 6'd12
99			`define state_addr_sel_sw_1 6'd13
100			`define state_addr_sel_sw_2 6'd14
101
102			`define state_xfer_key_1 6'd15
103			`define state_xfer_key_2 6'd16
104			`define state_pgm_start_key_1 6'd17
105			`define state_pgm_start_key_2 6'd18
106			`define state_pgm_stop_key_1 6'd19
107			`define state_pgm_stop_key_2 6'd20
108
109			`define state_read_gs_1 6'd31
110			`define state_read_gs_2 6'd32
111			`define state_read_gs_3 6'd33
112			`define state_read_gs_4 6'd34
113
114			`//-----------------------------------------------------------------------------`
115			`// Operator console state machine`
116			`//-----------------------------------------------------------------------------`
117			`always @(posedge rst, posedge dp) begin`
118			`if (rst) begin`
119			`console_to_addr <= 0;`
120			`pgm_start <= 0;`
121			`pgm_stop <= 0;`
122			`err_reset <= 0;`
123			`err_sense_reset <= 0;`
124			`man_pgm_reset <= 0;`
125			`man_acc_reset <= 0;`
126			`set_8000 <= 0;`
127			`reset_8000 <= 0;`
128
129			`// reset console switches`
130			`pgm_sw_stop <= 0;`
131			`pgm_sw_run <= 1;`
132			`ctl_sw_addr_stop <= 0;`
133			`ctl_sw_run <= 1;`
134			`ctl_sw_manual <= 0;`
135			`disp_sw_lacc <= 0;`
136			`disp_sw_uacc <= 0;`
137			`disp_sw_dist <= 1;`
138			`disp_sw_pgm <= 0;`
139			`disp_sw_ri <= 0;`
140			`disp_sw_ro <= 0;`
141			`ovflw_sw_stop <= 1;`
142			`ovflw_sw_sense <= 0;`
143			`err_sw_stop <= 1;`
144			`err_sw_sense <= 0;`
145
146			state <= `state_idle;
147			`busy <= 1;`
148			`digit_ready <= 0;`
149			cmd_digit_out <= `biq_blank;
150
151			`do_power_on_reset <= 1;`
152			`do_reset_console <= 0;`
153			`do_err_reset <= 0;`
154			`do_err_sense_reset <= 0;`
155			`do_pgm_reset <= 0;`
156			`do_acc_reset <= 0;`
157
158			`gs_ram_addr <= 15'd0;`
159
160			`end else begin`
161			`case (state)`
162			`state_idle: begin
163			`case (command)`
164			`cmd_none: begin
165			`if (do_power_on_reset) begin`
166			`do_power_on_reset <= 0;`
167			`do_reset_console <= 1;`
168			`do_pgm_reset <= 1;`
169			`do_acc_reset <= 1;`
170			`do_err_reset <= 1;`
171			`do_err_sense_reset <= 1;`
172			`end else if (do_reset_console) begin`
173			`do_reset_console <= 0;`
174			state <= `state_reset_console_1;
175			`end else if (do_pgm_reset) begin`
176			`do_pgm_reset <= 0;`
177			state <= `state_pgm_reset_1;
178			`end else if (do_acc_reset) begin`
179			`do_acc_reset <= 0;`
180			`man_acc_reset <= 1;`
181			state <= `state_acc_reset_1;
182			`end else if (do_err_reset) begin`
183			`do_err_reset <= 0;`
184			`err_reset <= 1;`
185			state <= `state_err_reset_1;
186			`end else if (do_err_sense_reset) begin`
187			`do_err_sense_reset <= 0;`
188			`err_sense_reset <= 1;`
189			state <= `state_err_sense_reset_1;
190			`end else begin`
191			`busy <= 0;`
192			`digit_ready <= 0;`
193			`end`
194			`end`
195
196			`cmd_pgm_sw_stop: begin
197			`busy <= 1;`
198			`pgm_sw_stop <= 1;`
199			`pgm_sw_run <= 0;`
200			`end`
201
202			`cmd_pgm_sw_run: begin
203			`busy <= 1;`
204			`pgm_sw_stop <= 0;`
205			`pgm_sw_run <= 1;`
206			`end`
207
208			`cmd_half_cycle_sw_run: begin
209			`busy <= 1;`
210			`half_cycle_sw_run <= 1;`
211			`half_cycle_sw_half <= 0;`
212			`end`
213
214			`cmd_half_cycle_sw_half: begin
215			`busy <= 1;`
216			`half_cycle_sw_run <= 0;`
217			`half_cycle_sw_half <= 1;`
218			`end`
219
220			`cmd_ctl_sw_addr_stop: begin
221			`busy <= 1;`
222			`ctl_sw_addr_stop <= 1;`
223			`ctl_sw_run <= 0;`
224			`ctl_sw_manual <= 0;`
225			`end`
226
227			`cmd_ctl_sw_run: begin
228			`busy <= 1;`
229			`ctl_sw_addr_stop <= 0;`
230			`ctl_sw_run <= 1;`
231			`ctl_sw_manual <= 0;`
232			`end`
233
234			`cmd_ctl_sw_manual: begin
235			`busy <= 1;`
236			`ctl_sw_addr_stop <= 0;`
237			`ctl_sw_run <= 0;`
238			`ctl_sw_manual <= 1;`
239			`end`
240
241			`cmd_disp_sw_lacc: begin
242			`busy <= 1;`
243			`disp_sw_lacc <= 1;`
244			`disp_sw_uacc <= 0;`
245			`disp_sw_dist <= 0;`
246			`disp_sw_pgm <= 0;`
247			`disp_sw_ri <= 0;`
248			`disp_sw_ro <= 0;`
249			`end`
250
251			`cmd_disp_sw_uacc: begin
252			`busy <= 1;`
253			`disp_sw_lacc <= 0;`
254			`disp_sw_uacc <= 1;`
255			`disp_sw_dist <= 0;`
256			`disp_sw_pgm <= 0;`
257			`disp_sw_ri <= 0;`
258			`disp_sw_ro <= 0;`
259			`end`
260
261			`cmd_disp_sw_dist: begin
262			`busy <= 1;`
263			`disp_sw_lacc <= 0;`
264			`disp_sw_uacc <= 0;`
265			`disp_sw_dist <= 1;`
266			`disp_sw_pgm <= 0;`
267			`disp_sw_ri <= 0;`
268			`disp_sw_ro <= 0;`
269			`end`
270
271			`cmd_disp_sw_prog: begin
272			`busy <= 1;`
273			`disp_sw_lacc <= 0;`
274			`disp_sw_uacc <= 0;`
275			`disp_sw_dist <= 0;`
276			`disp_sw_pgm <= 1;`
277			`disp_sw_ri <= 0;`
278			`disp_sw_ro <= 0;`
279			`end`
280
281			`cmd_disp_sw_ri: begin
282			`busy <= 1;`
283			`disp_sw_lacc <= 0;`
284			`disp_sw_uacc <= 0;`
285			`disp_sw_dist <= 0;`
286			`disp_sw_pgm <= 0;`
287			`disp_sw_ri <= 1;`
288			`disp_sw_ro <= 0;`
289			`end`
290
291			`cmd_disp_sw_ro: begin
292			`busy <= 1;`
293			`disp_sw_lacc <= 0;`
294			`disp_sw_uacc <= 0;`
295			`disp_sw_dist <= 0;`
296			`disp_sw_pgm <= 0;`
297			`disp_sw_ri <= 0;`
298			`disp_sw_ro <= 1;`
299			`end`
300
301			`cmd_ovflw_sw_stop: begin
302			`busy <= 1;`
303			`ovflw_sw_stop <= 1;`
304			`ovflw_sw_sense <= 0;`
305			`end`
306
307			`cmd_ovflw_sw_sense: begin
308			`busy <= 1;`
309			`ovflw_sw_stop <= 0;`
310			`ovflw_sw_sense <= 1;`
311			`end`
312
313			`cmd_err_sw_stop: begin
314			`busy <= 1;`
315			`err_sw_stop <= 1;`
316			`err_sw_sense <= 0;`
317			`end`
318
319			`cmd_err_sw_sense: begin
320			`busy <= 1;`
321			`err_sw_stop <= 0;`
322			`err_sw_sense <= 1;`
323			`end`
324
325			`cmd_storage_entry_sw: begin
326			`busy <= 1;`
327			state <= `state_storage_entry_sw_1;
328			`end`
329
330			`cmd_addr_sel_sw: begin
331			`busy <= 1;`
332			state <= `state_addr_sel_sw_1;
333			`end`
334
335			`cmd_xfer_key: begin
336			`if (ctl_sw_manual) begin`
337			`busy <= 1;`
338			state <= `state_xfer_key_1;
339			`end`
340			`end`
341
342			`cmd_pgm_start_key: begin
343			`busy <= 1;`
344			state <= `state_pgm_start_key_1;
345			`end`
346
347			`cmd_pgm_stop_key: begin
348			`busy <= 1;`
349			`pgm_stop <= 1;`
350			state <= `state_pgm_stop_key_1;
351			`end`
352
353			`cmd_pgm_reset_key: begin
354			`do_pgm_reset <= 1;`
355			`do_err_reset <= 1;`
356			`end`
357
358			`cmd_comp_reset_key: begin
359			`do_pgm_reset <= 1;`
360			`do_acc_reset <= 1;`
361			`do_err_reset <= 1;`
362			`end`
363
364			`cmd_acc_reset_key: begin
365			`do_acc_reset <= 1;`
366			`do_err_reset <= 1;`
367			`end`
368
369			`cmd_err_reset_key: begin
370			`do_err_reset <= 1;`
371			`end`
372
373			`cmd_err_sense_reset_key: begin
374			`do_err_sense_reset <= 1;`
375			`end`
376
377			`//--------------------------------------------------------------`
378			`// Read from general storage:`
379			`// --> 4 digits address, little-endian`
380			`// <-- 1 digit sign, 10 digits, little-endian`
381			`// 0 : Ignore if CPU not stopped`
382			`// Accept low-order address digit`
383			`// 1 : Accept remaining address digits`
384			`// 2 : Calculate word origin in gs RAM`
385			`// Validate address`
386			`// console_read_gs <= 1;`
387			`// 3 : Send gs-early digit to out`
388			`// digit_ready <= 1;`
389			`// 4 : digit_ready <= 0;`
390			`//--------------------------------------------------------------`
391			`cmd_read_gs: begin
392			`if (ctl_sw_manual) begin`
393			`busy <= 1;`
394			state <= `state_read_gs_1;
395			`end`
396			`end`
397			`ifdef 0
398			`cmd_write_gs:
399			`cmd_read_acc:
400			`cmd_read_dist:
401			`cmd_read_prog:
402			`cmd_clear_gs:
403			`cmd_load_gs:
404			`cmd_dump_gs:
405			`cmd_power_on_reset:
406			`cmd_reset_console:
407			`endif
408
409			`endcase;`
410			`end`
411
412			`// Reset console`
413			`state_reset_console_1: begin
414			if (d10) state <= `state_reset_console_2;
415			`end`
416
417			`state_reset_console_2: begin
418			storage_entry_sw[ontime_idx] <= d0? `biq_plus : `biq_0;
419			addr_sel_sw[ontime_idx[2:3]] <= `biq_0;
420			if (d10) state <= `state_idle;
421			`end`
422
423			`// Program reset key press`
424			`state_pgm_reset_1: begin
425			`if (wu & d10) begin`
426			`man_pgm_reset <= 1;`
427			state <= `state_pgm_reset_2;
428			`end`
429			`end`
430
431			`state_pgm_reset_2: begin
432			`if (wu & d10) begin`
433			`man_pgm_reset <= 0;`
434			state <= `state_idle;
435			`end`
436			`end`
437
438			`// Accumulator reset key press`
439			`state_acc_reset_1: begin
440			`if (wu & d10) begin`
441			`man_acc_reset <= 1;`
442			state <= `state_acc_reset_2;
443			`end`
444			`end`
445
446			`state_acc_reset_2: begin
447			`if (wu & d10) begin`
448			`man_acc_reset <= 0;`
449			state <= `state_idle;
450			`end`
451			`end`
452
453			`// Error reset key press`
454			`state_err_reset_1: begin
455			`if (wu & d10) begin`
456			`err_reset <= 1;`
457			state <= `state_err_reset_2;
458			`end`
459			`end`
460
461			`state_err_reset_2: begin
462			`if (wu & d10) begin`
463			`err_reset <= 0;`
464			state <= `state_idle;
465			`end`
466			`end`
467
468			`// Error sense reset key press`
469			`state_err_sense_reset_1: begin
470			`if (wu & d10) begin`
471			`err_sense_reset <= 1;`
472			state <= `state_err_sense_reset_2;
473			`end`
474			`end`
475
476			`state_err_sense_reset_2: begin
477			`if (wu & d10) begin`
478			`err_sense_reset <= 0;`
479			state <= `state_idle;
480			`end`
481			`end`
482
483			`// Set storage entry switches`
484			`state_storage_entry_sw_1: begin
485			`if (d0) begin`
486			state <= `state_storage_entry_sw_2;
487			`digit_ready <= 1;`
488			`storage_entry_sw[ontime_idx] <= cmd_digit_in;`
489			`end`
490			`end`
491
492			`state_storage_entry_sw_2: begin
493			`storage_entry_sw[ontime_idx] <= cmd_digit_in;`
494			`if (d10) begin`
495			state <= `state_idle;
496			`digit_ready <= 0;`
497			`end`
498			`end`
499
500			`// Set address selection switches`
501			`state_addr_sel_sw_1: begin
502			`if (dx) begin`
503			state <= `state_addr_sel_sw_2;
504			`digit_ready <= 1;`
505			`addr_sel_sw[ontime_idx[2:3]] <= cmd_digit_in;`
506			`end`
507			`end`
508
509			`state_addr_sel_sw_2: begin
510			`addr_sel_sw[ontime_idx[2:3]] <= cmd_digit_in;`
511			`if (d2) begin`
512			state <= `state_idle;
513			`digit_ready <= 0;`
514			`end`
515			`end`
516
517			`// Transfer key press`
518			`state_xfer_key_1: begin
519			`if (d10) begin`
520			`console_to_addr <= 1;`
521			state <= `state_xfer_key_2;
522			`end`
523			`end`
524
525			`state_xfer_key_2: begin
526			`if (d10) begin`
527			`console_to_addr <= 0;`
528			state <= `state_idle;
529			`end`
530			`end`
531
532			`// Start key press`
533			`state_pgm_start_key_1: begin
534			`if (wu & d10) begin`
535			`pgm_start <= 1;`
536			state <= `state_pgm_start_key_2;
537			`end`
538			`end`
539
540			`state_pgm_start_key_2: begin
541			`if (wu & d10) begin`
542			`pgm_start <= 0;`
543			state <= `state_idle;
544			`end`
545			`end`
546
547			`// Stop key press`
548			`state_pgm_stop_key_1: begin
549			if (hp) state <= `state_pgm_stop_key_2;
550			`end`
551
552			`state_pgm_stop_key_2: begin
553			`if (hp) begin`
554			`pgm_stop <= 0;`
555			state <= `state_idle;
556			`end`
557			`end`
558
559			`// Read word from general storage`
560			`// --> 4 digits address, little-endian`
561			`// <-- 1 digit sign, 10 digits, little-endian`
562			`// 0 : Ignore if CPU not stopped`
563			`// Accept low-order address digit`
564			`// 1 : Accept remaining address digits`
565			`// 2 : Calculate word origin in gs RAM`
566			`// Validate address`
567			`// console_read_gs <= 1;`
568			`// 3 : Send gs-early digit to out`
569			`// digit_ready <= 1;`
570			`// 4 : digit_ready <= 0;`
571			`state_read_gs_1: begin
572			`if (dx) begin`
573			state <= `state_read_gs_2;
574			`digit_ready <= 1;`
575			`gs_addr_u <= cmd_digit_in;`
576			`end`
577			`end`
578
579			`state_read_gs_2: begin
580			`if (d0) gs_addr_t <= cmd_digit_in;`
581			`else if (d1) gs_addr_h <= cmd_digit_in;`
582			`else if (d2) begin`
583			`gs_addr_th <= cmd_digit_in;`
584			state <= `state_read_gs_3;
585			`digit_ready <= 0;`
586			`end`
587			`end`
588
589			`state_read_gs_3: begin
590			`gs_ram_addr <= gs_word_addr;`
591			state <= `state_read_gs_4;
592			`end`
593
594			`endcase;`
595			`end`
596			`end;`
597
598			`always @(posedge rst, posedge ap) begin`
599			`if (rst) begin`
600			data_out <= `biq_blank;
601			addr_out <= `biq_blank;
602			`end else begin`
603			data_out <= d10? `biq_blank : storage_entry_sw[early_idx];
604			addr_out <= (d3 \| d4 \| d5 \| d6)? addr_sel_sw[early_idx[2:3]] : `biq_blank;
605			`end`
606			`end;`
607
608			`always @(posedge rst, posedge ap) begin`
609			`if (rst) begin`
610			`punch_card <= 0;`
611			`read_card <= 0;`
612			`card_digit_ready <= 0;`
613			`end`
614			`end;`
615
616			`endmodule`