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eightycc |
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// IBM 650 Reconstruction in Verilog (i650)
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//
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// This file is part of the IBM 650 Reconstruction in Verilog (i650) project
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// http:////www.opencores.org/project,i650
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//
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// Description: Program step register.
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//
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// Additional Comments: See US 2959351, Fig. 62.
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//
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// Copyright (c) 2015 Robert Abeles
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//
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// This source file is free software; you can redistribute it
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// and/or modify it under the terms of the GNU Lesser General
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// Public License as published by the Free Software Foundation;
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// either version 2.1 of the License, or (at your option) any
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// later version.
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//
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// This source is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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// PURPOSE. See the GNU Lesser General Public License for more
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// details.
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//
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// You should have received a copy of the GNU Lesser General
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// Public License along with this source; if not, download it
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// from http://www.opencores.org/lgpl.shtml
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//////////////////////////////////////////////////////////////////////////////////
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`include "defines.v"
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module prog_step (
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input rst,
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input ap, dp,
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input dx, d0, d10,
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input [0:3] early_idx, ontime_idx,
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input man_prog_reset, rips,
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input [0:6] adder_out, sel_store_out,
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input prog_ped_regen, prog_add, // see tlu 86d
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output reg [0:6] early_out, ontime_out,
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output [0:6] ped_out,
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output prog_restart_sig
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);
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reg [0:6] digits [0:15];
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reg ri_prog_step;
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//-----------------------------------------------------------------------------
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// AP -- Read digits RAM, write early and ontime outs
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// Start/stop RI control
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// Generate prog_restart_sig
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//-----------------------------------------------------------------------------
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digit_pulse pr_sig (rst, ap, ~rips, 1'b1, prog_restart_sig);
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always @(posedge ap)
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if (rst) begin
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ri_prog_step <= 0;
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early_out <= `biq_blank;
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ontime_out <= `biq_blank;
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end else begin
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if (d0) begin
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ri_prog_step <= rips;
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end
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early_out <= (dx | d10)? `biq_blank : digits[early_idx];
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ontime_out <= man_prog_reset? `biq_0 : early_out;
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end;
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//-----------------------------------------------------------------------------
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// DP
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//-----------------------------------------------------------------------------
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assign ped_out = ri_prog_step? sel_store_out
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: prog_ped_regen? ontime_out
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: prog_add? adder_out
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: `biq_blank;
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always @(posedge dp)
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digits[ontime_idx] <= (dx | d0)? `biq_blank : ped_out;
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endmodule
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