OpenCores
URL https://opencores.org/ocsvn/i650/i650/trunk

Subversion Repositories i650

[/] [i650/] [trunk/] [rtl/] [timing.v] - Blame information for rev 5

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 5 eightycc 
`timescale 1ns / 1ps
2 
//////////////////////////////////////////////////////////////////////////////////
3 
// IBM 650 Reconstruction in Verilog (i650)
4 
//
5 
// This file is part of the IBM 650 Reconstruction in Verilog (i650) project
6 
// http:////www.opencores.org/project,i650
7 
//
8 
// Description: 650 Timing.
9 
//
10 
// Additional Comments: See US 2959351, Fig. 53, 54 and 55. Additional index
11 
//  counters provided to address general storage and register RAMs.
12 
//
13 
// Copyright (c) 2015 Robert Abeles
14 
//
15 
// This source file is free software; you can redistribute it
16 
// and/or modify it under the terms of the GNU Lesser General
17 
// Public License as published by the Free Software Foundation;
18 
// either version 2.1 of the License, or (at your option) any
19 
// later version.
20 
//
21 
// This source is distributed in the hope that it will be
22 
// useful, but WITHOUT ANY WARRANTY; without even the implied
23 
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
24 
// PURPOSE.  See the GNU Lesser General Public License for more
25 
// details.
26 
//
27 
// You should have received a copy of the GNU Lesser General
28 
// Public License along with this source; if not, download it
29 
// from http://www.opencores.org/lgpl.shtml
30 
//////////////////////////////////////////////////////////////////////////////////
31 
module timing (
32 
      input clk,
33 
      input rst,
34 
      output reg ap, bp, cp, dp,
35 
      output reg dx, d0, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10,
36 
      output reg d1_d5, d5_dx, d5_d10, d1_dx, d5_d9, d10_d1_d5,
37 
      //output reg dxcu_d1cu, d10cl_d0cu,
38 
           output dxl, dxu, d0l, d0u, d1l, d1u, d2l, d10u,
39 
           output reg w0, w1, w2, w3, w4, w5, w6, w7, w8, w9,
40 
           output reg wl, wu, ewl,
41 
           output reg s0, s1, s2, s3, s4,
42 
           output reg hp,
43 
 
44 
           output reg[0:9] digit_idx,
45 
           output reg[0:3] early_idx, ontime_idx
46 
   );
47 
 
48 
        reg[0:3] digit_ctr;
49 
        reg[0:3] word_ctr;
50 
        reg[0:2] sector_ctr;
51 
 
52 
        assign dxl = dx & wl;
53 
        assign dxu = dx & wu;
54 
        assign d0l = d0 & wl;
55 
        assign d0u = d0 & wu;
56 
        assign d1l = d1 & wl;
57 
        assign d1u = d1 & wu;
58 
        assign d2l = d2 & wl;
59 
        assign d10u = d10 & wu;
60 
 
61 
        //-----------------------------------------------------------------------------
62 
        // 650 four-phase clock
63 
        //-----------------------------------------------------------------------------
64 
        always @(posedge rst, posedge clk) begin
65 
                if (rst) begin
66 
                        ap <= 1;
67 
                        bp <= 0;
68 
                        cp <= 0;
69 
                        dp <= 0;
70 
                end else begin
71 
                        ap <= dp;
72 
                        bp <= ap;
73 
                        cp <= bp;
74 
                        dp <= cp;
75 
                end;
76 
        end;
77 
 
78 
        //-----------------------------------------------------------------------------
79 
        // Counter-based timing signals
80 
        //-----------------------------------------------------------------------------
81 
        always @(posedge rst, posedge dp) begin
82 
                if (rst) begin
83 
                        dx <= 0;
84 
                        d0 <= 0;
85 
                        d1 <= 0;
86 
                        d2 <= 0;
87 
                        d3 <= 0;
88 
                        d4 <= 0;
89 
                        d5 <= 0;
90 
                        d6 <= 0;
91 
                        d7 <= 0;
92 
                        d8 <= 0;
93 
                        d9 <= 0;
94 
                        d10 <= 0;
95 
                        d1_d5 <= 0;
96 
                        d5_dx <= 0;
97 
                        d5_d10 <= 0;
98 
                        d1_dx <= 0;
99 
                        d5_d9 <= 0;
100 
                        d10_d1_d5 <= 0;
101 
                        w0 <= 0;
102 
                        w1 <= 0;
103 
                        w2 <= 0;
104 
                        w3 <= 0;
105 
                        w4 <= 0;
106 
                        w5 <= 0;
107 
                        w6 <= 0;
108 
                        w7 <= 0;
109 
                        w8 <= 0;
110 
                        w9 <= 0;
111 
                        wu <= 0;
112 
                        wl <= 0;
113 
                        ewl <= 0;
114 
                        s0 <= 0;
115 
                        s1 <= 0;
116 
                        s2 <= 0;
117 
                        s3 <= 0;
118 
                        s4 <= 0;
119 
                        hp <= 0;
120 
                        digit_ctr <= 4'd0;
121 
                        word_ctr  <= 4'd0;
122 
                        sector_ctr <= 4'd0;
123 
                        digit_idx <= 10'd599;
124 
                        early_idx <= 4'd10;
125 
                        ontime_idx <= 4'd11;
126 
                end else begin
127 
                        digit_idx <= (digit_idx + 1) % 600;
128 
                        early_idx <= (early_idx + 1) % 12;
129 
                        ontime_idx <= (ontime_idx + 1) % 12;
130 
                        digit_ctr <= (digit_ctr + 1) % 12;
131 
                        if (digit_ctr == 4'd11) begin
132 
                                word_ctr <= (word_ctr + 1) % 10;
133 
                                if (word_ctr == 9) begin
134 
                                        sector_ctr <= (sector_ctr + 1) % 5;
135 
                                end;
136 
                        end;
137 
 
138 
                   case (digit_ctr)
139 
                      4'd0: begin
140 
                               d10 <= 0; dx <= 1;
141 
                                                        d5_dx <= 0;
142 
                                                        d1_dx <= 0;
143 
                                                        d10_d1_d5 <= 0;
144 
                                                        wl <= ~word_ctr[3];
145 
                                                        wu <=  word_ctr[3];
146 
                                                        case (word_ctr)
147 
                                                                4'd0: begin
148 
                                                                                        w9 <= 0; w0 <= 1;
149 
                                                                                        case (sector_ctr)
150 
                                                                                                3'd0: begin
151 
                                                                                                                        s4 <= 0; s0 <= 1;
152 
                                                                                                                        hp <= 1;
153 
                                                                                                      end
154 
                                                                                                3'd1: begin
155 
                                                                                                                        s0 <= 0; s1 <= 1;
156 
                                                                                                      end
157 
                                                                                                3'd2: begin
158 
                                                                                                                        s1 <= 0; s2 <= 1;
159 
                                                                                                      end
160 
                                                                                                3'd3: begin
161 
                                                                                                                        s2 <= 0; s3 <= 1;
162 
                                                                                                      end
163 
                                                                                                3'd4: begin
164 
                                                                                                                        s3 <= 0; s4 <= 1;
165 
                                                                                                      end
166 
                                                                                        endcase;
167 
                                                                                end
168 
                                                                4'd1: begin
169 
                                                                                        w0 <= 0; w1 <= 1;
170 
                                                                                end
171 
                                                                4'd2: begin
172 
                                                                                        w1 <= 0; w2 <= 1;
173 
                                                                                end
174 
                                                                4'd3: begin
175 
                                                                                        w2 <= 0; w3 <= 1;
176 
                                                                                end
177 
                                                                4'd4: begin
178 
                                                                                        w3 <= 0; w4 <= 1;
179 
                                                                                end
180 
                                                                4'd5: begin
181 
                                                                                        w4 <= 0; w5 <= 1;
182 
                                                                                end
183 
                                                                4'd6: begin
184 
                                                                                        w5 <= 0; w6 <= 1;
185 
                                                                                end
186 
                                                                4'd7: begin
187 
                                                                                        w6 <= 0; w7 <= 1;
188 
                                                                                end
189 
                                                                4'd8: begin
190 
                                                                                        w7 <= 0; w8 <= 1;
191 
                                                                                end
192 
                                                                4'd9: begin
193 
                                                                                        w8 <= 0; w9 <= 1;
194 
                                                                                end
195 
                                                        endcase;
196 
                            end
197 
                      4'd1: begin
198 
                               dx <= 0; d0 <= 1;
199 
                                                        hp <= 0;
200 
                            end
201 
                      4'd2: begin
202 
                               d0 <= 0; d1 <= 1;
203 
                                                        d1_d5 <= 1;
204 
                            end
205 
                      4'd3: begin
206 
                               d1 <= 0; d2 <= 1;
207 
                                                        d1_dx <= 1;
208 
                                                        d10_d1_d5 <= 1;
209 
                            end
210 
                      4'd4: begin
211 
                               d2 <= 0; d3 <= 1;
212 
                            end
213 
                      4'd5: begin
214 
                               d3 <= 0; d4 <= 1;
215 
                               ewl <= wu;
216 
                            end
217 
                      4'd6: begin
218 
                               d4 <= 0; d5 <= 1;
219 
                                                        d1_d5 <= 0;
220 
                                                        d10_d1_d5 <= 0;
221 
                                                        d5_dx <= 1;
222 
                                                        d5_d10 <= 1;
223 
                                                        d5_d9 <= 1;
224 
                            end
225 
                      4'd7: begin
226 
                               d5 <= 0; d6 <= 1;
227 
                            end
228 
                      4'd8: begin
229 
                               d6 <= 0; d7 <= 1;
230 
                            end
231 
                      4'd9: begin
232 
                               d7 <= 0; d8 <= 1;
233 
                            end
234 
                      4'd10: begin
235 
                               d8 <= 0; d9 <= 1;
236 
                                                        d5_d9 <= 0;
237 
                            end
238 
                      4'd11: begin
239 
                               d9 <= 0; d10 <= 1;
240 
                                                        d5_d10 <= 0;
241 
                                                        d10_d1_d5 <= 1;
242 
                            end
243 
                   endcase;
244 
                end;
245 
        end;
246 
 
247 
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.