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1 12 eightycc
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// IBM 650 Reconstruction in Verilog (i650)
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// 
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// This file is part of the IBM 650 Reconstruction in Verilog (i650) project
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// http:////www.opencores.org/project,i650
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//
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// Description: Top level.
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// 
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// Additional Comments: See US 2959351, Fig. 53, 54 and 55. Additional index
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//  counters provided to address general storage and register RAMs.
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//
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// Copyright (c) 2015 Robert Abeles
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//
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// This source file is free software; you can redistribute it
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// and/or modify it under the terms of the GNU Lesser General
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// Public License as published by the Free Software Foundation;
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// either version 2.1 of the License, or (at your option) any
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// later version.
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//
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// This source is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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// PURPOSE.  See the GNU Lesser General Public License for more
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// details.
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//
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// You should have received a copy of the GNU Lesser General
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// Public License along with this source; if not, download it
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// from http://www.opencores.org/lgpl.shtml
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//////////////////////////////////////////////////////////////////////////////////
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`include "defines.v"
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module toplev (
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      input clk,
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      input rst,
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      input [0:6] cmd_digit_in, io_buffer_in,
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      input [0:5] command,
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      output [0:6] cmd_digit_out, display_digit,
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      output busy, digit_ready, punch_card, read_card, card_digit_ready,
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      output digit_sync, word_upper,
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      output [0:3] digit_ctr
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  );
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46 13 eightycc
   wire ap, bp, cp, dp;
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   wire dx, d0, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10,
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        d1_d5, d5_dx, d5_d10, d1_dx, d5_d9, d10_d1_d5,
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        dxl, dxu, d0l, d0u, d1l, d1u, d2l, d10u;
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   wire w0, w1, w2, w3, w4, w5, w6, w7, w8, w9,
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        wl, wu, ewl;
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   wire s0, s1, s2, s3, s4, hp;
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   wire [0:9] digit_idx;
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   wire [0:3] early_idx, ontime_idx;
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   assign digit_sync = bp;
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   assign digit_ctr = ontime_idx;
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   assign word_upper = wu;
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   timing tm (
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    .clk(clk),
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    .rst(rst),
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    .ap(ap),
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    .bp(bp),
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    .cp(cp),
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    .dp(dp),
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    .dx(dx),
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    .d0(d0),
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    .d1(d1),
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    .d2(d2),
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    .d3(d3),
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    .d4(d4),
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    .d5(d5),
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    .d6(d6),
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    .d7(d7),
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    .d8(d8),
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    .d9(d9),
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    .d10(d10),
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    .d1_d5(d1_d5),
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    .d5_dx(d5_dx),
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    .d5_d10(d5_d10),
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    .d1_dx(d1_dx),
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    .d5_d9(d5_d9),
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    .d10_d1_d5(d10_d1_d5),
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    .dxl(dxl),
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    .dxu(dxu),
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    .d0l(d0l),
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    .d0u(d0u),
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    .d1l(d1l),
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    .d1u(d1u),
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    .d2l(d2l),
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    .d10u(d10u),
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    .w0(w0),
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    .w1(w1),
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    .w2(w2),
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    .w3(w3),
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    .w4(w4),
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    .w5(w5),
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    .w6(w6),
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    .w7(w7),
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    .w8(w8),
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    .w9(w9),
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    .wl(wl),
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    .wu(wu),
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    .ewl(ewl),
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    .s0(s0),
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    .s1(s1),
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    .s2(s2),
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    .s3(s3),
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    .s4(s4),
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    .hp(hp),
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    .digit_idx(digit_idx),
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    .early_idx(early_idx),
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    .ontime_idx(ontime_idx)
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   );
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117 12 eightycc
   //-----------------------------------------------------------------------------
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   // Accumulator
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   //-----------------------------------------------------------------------------
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   wire [0:6] ac_early_out, ac_ontime_out, ac_ped_out;
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   //-----------------------------------------------------------------------------
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   // General storage
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   //-----------------------------------------------------------------------------
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   wire [0:4] gs_out;
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   wire gs_double_write, gs_no_write;
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   //-----------------------------------------------------------------------------
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   // Operator controls
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   //-----------------------------------------------------------------------------
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   wire [0:6] oc_data_out, oc_addr_out, oc_console_out, oc_display_digit;
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   wire oc_console_to_addr;
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   wire [0:14] oc_gs_ram_addr;
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   wire oc_read_gs, oc_write_gs;
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   wire oc_pgm_start, oc_pgm_stop, oc_err_reset, oc_err_sense_reset;
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   wire oc_run_control, oc_half_or_pgm_stop, oc_ri_storage, oc_ro_storage,
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        oc_storage_control;
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   wire oc_man_pgm_reset, oc_man_acc_reset, oc_set_8000, oc_reset_8000,
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        oc_hard_reset;
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   assign display_digit = oc_display_digit;
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   //-----------------------------------------------------------------------------
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   // Translators
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   //-----------------------------------------------------------------------------
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   wire tr_gs_write;
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   wire [0:4] tr_gs_in;
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   wire [0:6] tr_select_out;
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   accumulator ac (
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    .rst(rst),
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    .ap(ap),
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    .bp(bp),
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    .dp(dp),
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    .d1(d1),
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    .d2(d2),
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    .d10(d10),
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    .dxu(dxu),
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    .d0u(d0u),
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    .wu(wu),
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    .wl(wl),
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    .adder_out(`biq_0),
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    .acc_regen_gate(1'b1),
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    .right_shift_gate(1'b0),
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    .acc_ri_gate(1'b0),
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    .zero_shift_count(1'b0),
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    .man_acc_reset(oc_man_acc_reset),
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    .reset_op_latch(1'b0),
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    .early_idx(early_idx),
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    .ontime_idx(ontime_idx),
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    .early_out(ac_early_out),
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    .ontime_out(ac_ontime_out),
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    .ped_out(ac_ped_out)
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    );
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175 13 eightycc
   gen_store gs (
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    .rst(oc_hard_reset),
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    .ap(ap),
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    .dp(dp),
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    .write_gate(tr_gs_write),
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    .addr_th(`biq_blank),
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    .addr_h(`biq_blank),
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    .addr_t(`biq_blank),
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    .dynamic_addr(digit_idx),
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    .gs_in(tr_gs_in),
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    .console_ram_addr(oc_gs_ram_addr),
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    .console_read_gs(oc_read_gs),
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    .console_write_gs(oc_write_gs),
188 12 eightycc
    .gs_out(gs_out),
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    .double_write(gs_double_write),
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    .no_write(gs_no_write)
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    );
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193 13 eightycc
   operator_ctl oc (
194 12 eightycc
    .rst(rst),
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    .clk(clk),
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    .ap(ap),
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    .dp(dp),
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    .dx(dx),
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    .d0(d0),
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    .d1(d1),
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    .d2(d2),
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    .d3(d3),
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    .d4(d4),
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    .d5(d5),
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    .d6(d6),
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    .d10(d10),
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    .wu(wu),
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    .hp(hp),
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    .early_idx(early_idx),
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    .ontime_idx(ontime_idx),
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    .cmd_digit_in(cmd_digit_in),
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    .io_buffer_in(io_buffer_in),
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    .gs_in(tr_select_out),
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    .acc_ontime(ac_ontime_out),
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    .dist_ontime(`biq_blank),
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    .prog_ontime(`biq_blank),
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    .command(command),
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    .data_out(oc_data_out),
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    .addr_out(oc_addr_out),
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    .console_out(oc_console_out),
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    .display_digit(oc_display_digit),
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    .console_to_addr(oc_console_to_addr),
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    .gs_ram_addr(oc_gs_ram_addr),
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    .read_gs(oc_read_gs),
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    .write_gs(oc_write_gs),
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    .pgm_start(oc_pgm_start),
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    .pgm_stop(oc_pgm_stop),
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    .err_reset(oc_err_reset),
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    .err_sense_reset(oc_err_sense_reset),
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    .run_control(oc_run_control),
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    .half_or_pgm_stop(oc_half_or_pgm_stop),
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    .ri_storage(oc_ri_storage),
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    .ro_storage(oc_ro_storage),
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    .storage_control(oc_storage_control),
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    .man_pgm_reset(oc_man_pgm_reset),
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    .man_acc_reset(oc_man_acc_reset),
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    .set_8000(oc_set_8000),
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    .reset_8000(oc_reset_8000),
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    .hard_reset(oc_hard_reset),
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    .cmd_digit_out(cmd_digit_out),
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    .busy(busy),
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    .digit_ready(digit_ready),
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    .punch_card(punch_card),
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    .read_card(read_card),
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    .card_digit_ready(card_digit_ready)
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    );
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248 13 eightycc
    translators tr (
249 12 eightycc
    .dist_early_out(`biq_blank),
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    .bs_out(`biq_blank),
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    .console_out(oc_console_out),
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    .ri_gs(1'b0),
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    .ri_bs(1'b0),
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    .ri_console(oc_write_gs),
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    .n800x(1'b1),
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    .gs_out(gs_out),
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    .gs_write(tr_gs_write),
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    .gs_in(tr_gs_in),
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    .select_out(tr_select_out)
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    );
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endmodule

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