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eightycc |
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// IBM 650 Reconstruction in Verilog (i650)
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//
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// This file is part of the IBM 650 Reconstruction in Verilog (i650) project
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// http:////www.opencores.org/project,i650
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//
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// Description: Accumulator zero check.
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//
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// Additional Comments: See US 2959351, Fig. 84.
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//
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// Copyright (c) 2015 Robert Abeles
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//
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// This source file is free software; you can redistribute it
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// and/or modify it under the terms of the GNU Lesser General
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// Public License as published by the Free Software Foundation;
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// either version 2.1 of the License, or (at your option) any
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// later version.
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//
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// This source is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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// PURPOSE. See the GNU Lesser General Public License for more
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// details.
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//
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// You should have received a copy of the GNU Lesser General
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// Public License along with this source; if not, download it
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// from http://www.opencores.org/lgpl.shtml
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//////////////////////////////////////////////////////////////////////////////////
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`include "defines.v"
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module zero_check (
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input rst,
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input bp,
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input d0, d1_dx,
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input wu,
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input acc_no_zero,
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output acc_no_zero_test, acc_zero_test
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);
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reg no_zero_latch, no_zero_check_latch;
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assign acc_no_zero_test = no_zero_latch & no_zero_check_latch;
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assign acc_zero_test = ~no_zero_latch & ~no_zero_check_latch;
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always @(posedge bp)
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if (rst) begin
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no_zero_latch <= 0;
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no_zero_check_latch <= 0;
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end else if (wu & d0) begin
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no_zero_latch <= 0;
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no_zero_check_latch <= 0;
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end else if (acc_no_zero & d1_dx) begin
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no_zero_latch <= 1;
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no_zero_check_latch <= 1;
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end;
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endmodule
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