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ENTITY fulladder IS

PORT (

  a      : in  BIT;

  b      : in  BIT;

  cin    : in  BIT;

  cout   : out BIT;

  sout   : out BIT;

  vdd    : in  BIT;

  vss    : in  BIT

);

END fulladder ;

ARCHITECTURE behaviour_data_flow OF fulladder IS

BEGIN

  ASSERT ((vdd and not (vss)) = '1')

  REPORT "power supply is missing on fulladder"

  SEVERITY WARNING;

  cout <= (a and b) or ((a xor b) and cin);

  sout <= (a xor b) xor cin;

END;