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-- VHDL data flow description generated from `heart_ctrlr`

--              date : Fri Aug 24 20:54:23 2001

-- Entity Declaration

ENTITY heart_ctrlr IS

  PORT (

  ck : in BIT;  -- ck

  reset : in BIT;       -- reset

  start : in BIT;       -- start

  key_ready : in BIT;   -- key_ready

  round : in bit_vector(2 DOWNTO 0) ;   -- round

  en1 : out BIT;        -- en1

  en2 : out BIT;        -- en2

  en3 : out BIT;        -- en3

  en4 : out BIT;        -- en4

  en5 : out BIT;        -- en5

  en6 : out BIT;        -- en6

  en7 : out BIT;        -- en7

  en_out : out BIT;     -- en_out

  en_key_out : out BIT; -- en_key_out

  en_key_out9 : out BIT;        -- en_key_out9

  sel_in : out BIT;     -- sel_in

  ck_crnd : out BIT;    -- ck_crnd

  finish : out BIT;     -- finish

  vdd : in BIT; -- vdd

  vss : in BIT  -- vss

  );

END heart_ctrlr;

-- Architecture Declaration

ARCHITECTURE VBE OF heart_ctrlr IS

  SIGNAL current_state : REG_VECTOR(4 DOWNTO 0) REGISTER;       -- current_state

  SIGNAL current_state_s17 : BIT;               -- current_state_s17

  SIGNAL next_state_s17 : BIT;          -- next_state_s17

  SIGNAL current_state_s16 : BIT;               -- current_state_s16

  SIGNAL next_state_s16 : BIT;          -- next_state_s16

  SIGNAL current_state_s15 : BIT;               -- current_state_s15

  SIGNAL next_state_s15 : BIT;          -- next_state_s15

  SIGNAL current_state_s14 : BIT;               -- current_state_s14

  SIGNAL next_state_s14 : BIT;          -- next_state_s14

  SIGNAL current_state_s13 : BIT;               -- current_state_s13

  SIGNAL next_state_s13 : BIT;          -- next_state_s13

  SIGNAL current_state_s12 : BIT;               -- current_state_s12

  SIGNAL next_state_s12 : BIT;          -- next_state_s12

  SIGNAL current_state_s11 : BIT;               -- current_state_s11

  SIGNAL next_state_s11 : BIT;          -- next_state_s11

  SIGNAL current_state_s10 : BIT;               -- current_state_s10

  SIGNAL next_state_s10 : BIT;          -- next_state_s10

  SIGNAL current_state_s9 : BIT;                -- current_state_s9

  SIGNAL next_state_s9 : BIT;           -- next_state_s9

  SIGNAL current_state_s8 : BIT;                -- current_state_s8

  SIGNAL next_state_s8 : BIT;           -- next_state_s8

  SIGNAL current_state_s7 : BIT;                -- current_state_s7

  SIGNAL next_state_s7 : BIT;           -- next_state_s7

  SIGNAL current_state_s6 : BIT;                -- current_state_s6

  SIGNAL next_state_s6 : BIT;           -- next_state_s6

  SIGNAL current_state_s5 : BIT;                -- current_state_s5

  SIGNAL next_state_s5 : BIT;           -- next_state_s5

  SIGNAL current_state_s4 : BIT;                -- current_state_s4

  SIGNAL next_state_s4 : BIT;           -- next_state_s4

  SIGNAL current_state_s3 : BIT;                -- current_state_s3

  SIGNAL next_state_s3 : BIT;           -- next_state_s3

  SIGNAL current_state_s2 : BIT;                -- current_state_s2

  SIGNAL next_state_s2 : BIT;           -- next_state_s2

  SIGNAL current_state_s1 : BIT;                -- current_state_s1

  SIGNAL next_state_s1 : BIT;           -- next_state_s1

  SIGNAL current_state_s0 : BIT;                -- current_state_s0

  SIGNAL next_state_s0 : BIT;           -- next_state_s0

  SIGNAL next_state : BIT_VECTOR(4 DOWNTO 0);   -- next_state

BEGIN

  next_state(0) <= (next_state_s2 OR next_state_s3 OR next_state_s4

OR next_state_s5 OR next_state_s6 OR next_state_s9

OR next_state_s11 OR next_state_s15);

  next_state(1) <= (next_state_s1 OR next_state_s3 OR next_state_s4

OR next_state_s8 OR next_state_s9 OR next_state_s10

 OR next_state_s12 OR next_state_s15 OR

next_state_s16 OR next_state_s17);

  next_state(2) <= (next_state_s3 OR next_state_s5 OR next_state_s8

OR next_state_s11 OR next_state_s12 OR

next_state_s13 OR next_state_s14);

  next_state(3) <= (next_state_s1 OR next_state_s3 OR next_state_s4

OR next_state_s5 OR next_state_s6 OR next_state_s7

OR next_state_s11 OR next_state_s14 OR

next_state_s17);

  next_state(4) <= (next_state_s0 OR next_state_s2 OR next_state_s6

OR next_state_s7 OR next_state_s9 OR next_state_s10

 OR next_state_s11 OR next_state_s12 OR

next_state_s14 OR next_state_s17);

  next_state_s0 <= ((current_state_s0 AND (NOT(key_ready) OR NOT(

start))) OR current_state_s17 OR (current_state_s7 AND

 (NOT(round(0)) OR NOT(round(1)) OR NOT(round(2)))

));

  current_state_s0 <= (current_state(4) AND NOT(current_state(3)) AND

NOT(current_state(1)) AND NOT(current_state(0)));

  next_state_s1 <= (current_state_s0 AND key_ready AND start);

  current_state_s1 <= (NOT(current_state(4)) AND current_state(3) AND

NOT(current_state(2)) AND NOT(current_state(0)));

  next_state_s2 <= current_state_s1;

  current_state_s2 <= (current_state(4) AND NOT(current_state(3)) AND

NOT(current_state(1)) AND current_state(0));

  next_state_s3 <= current_state_s2;

  current_state_s3 <= (NOT(current_state(4)) AND current_state(3) AND

current_state(2) AND current_state(1));

  next_state_s4 <= current_state_s3;

  current_state_s4 <= (NOT(current_state(4)) AND current_state(3) AND

NOT(current_state(2)) AND current_state(0));

  next_state_s5 <= current_state_s4;

  current_state_s5 <= (NOT(current_state(4)) AND current_state(3) AND

current_state(2) AND NOT(current_state(1)));

  next_state_s6 <= current_state_s5;

  current_state_s6 <= (current_state(4) AND current_state(3) AND NOT(

current_state(2)) AND current_state(0));

  next_state_s7 <= current_state_s6;

  current_state_s7 <= (current_state(3) AND NOT(current_state(2)) AND

NOT(current_state(1)) AND NOT(current_state(0)));

  next_state_s8 <= (current_state_s7 AND round(0) AND round(1) AND

round(2));

  current_state_s8 <= (NOT(current_state(4)) AND NOT(current_state(3))

AND current_state(2) AND current_state(1));

  next_state_s9 <= current_state_s8;

  current_state_s9 <= (current_state(4) AND NOT(current_state(3)) AND

current_state(1) AND current_state(0));

  next_state_s10 <= current_state_s9;

  current_state_s10 <= (current_state(4) AND NOT(current_state(3)) AND

NOT(current_state(2)) AND current_state(1) AND NOT(

current_state(0)));

  next_state_s11 <= current_state_s10;

  current_state_s11 <= (current_state(4) AND current_state(3) AND

current_state(2) AND current_state(0));

  next_state_s12 <= current_state_s11;

  current_state_s12 <= (current_state(4) AND NOT(current_state(3)) AND

current_state(2) AND current_state(1));

  next_state_s13 <= current_state_s12;

  current_state_s13 <= (NOT(current_state(4)) AND NOT(current_state(3))

AND current_state(2) AND NOT(current_state(1)));

  next_state_s14 <= current_state_s13;

  current_state_s14 <= (current_state(4) AND current_state(3) AND

current_state(2) AND NOT(current_state(0)));

  next_state_s15 <= current_state_s14;

  current_state_s15 <= (NOT(current_state(4)) AND NOT(current_state(3))

AND NOT(current_state(2)) AND current_state(0));

  next_state_s16 <= current_state_s15;

  current_state_s16 <= (NOT(current_state(4)) AND NOT(current_state(3))

AND NOT(current_state(2)) AND NOT(current_state(0)));

  next_state_s17 <= current_state_s16;

  current_state_s17 <= (current_state(4) AND current_state(3) AND NOT(

current_state(2)) AND current_state(1));

  label0 : BLOCK ((NOT((ck'STABLE)) AND ck) = '1')

  BEGIN

    current_state(0) <= GUARDED (next_state(0) AND NOT(reset));

  END BLOCK label0;

  label1 : BLOCK ((NOT((ck'STABLE)) AND ck) = '1')

  BEGIN

    current_state(1) <= GUARDED (next_state(1) AND NOT(reset));

  END BLOCK label1;

  label2 : BLOCK ((NOT((ck'STABLE)) AND ck) = '1')

  BEGIN

    current_state(2) <= GUARDED (next_state(2) AND NOT(reset));

  END BLOCK label2;

  label3 : BLOCK ((NOT((ck'STABLE)) AND ck) = '1')

  BEGIN

    current_state(3) <= GUARDED (next_state(3) AND NOT(reset));

  END BLOCK label3;

  label4 : BLOCK ((NOT((ck'STABLE)) AND ck) = '1')

  BEGIN

    current_state(4) <= GUARDED (next_state(4) OR reset);

  END BLOCK label4;

finish <= (current_state_s17 AND NOT(reset));

ck_crnd <= ((current_state_s6 AND NOT(reset)) OR (

current_state_s17 AND NOT(reset)));

sel_in <= (current_state_s0 AND (round(0) OR round(1) OR

round(2)) AND key_ready AND start AND NOT(reset));

en_key_out9 <= (current_state_s15 AND NOT(reset));

en_key_out <= ((current_state_s0 AND key_ready AND start AND

NOT(reset)) OR (current_state_s8 AND NOT(reset)));

en_out <= (current_state_s16 AND NOT(reset));

en7 <= ((current_state_s7 AND NOT(reset)) OR (

current_state_s15 AND NOT(reset)));

en6 <= ((current_state_s6 AND NOT(reset)) OR (

current_state_s14 AND NOT(reset)));

en5 <= ((current_state_s5 AND NOT(reset)) OR (

current_state_s13 AND NOT(reset)));

en4 <= ((current_state_s4 AND NOT(reset)) OR (

current_state_s12 AND NOT(reset)));

en3 <= ((current_state_s3 AND NOT(reset)) OR (

current_state_s11 AND NOT(reset)));

en2 <= ((current_state_s2 AND NOT(reset)) OR (

current_state_s10 AND NOT(reset)));

en1 <= ((current_state_s1 AND NOT(reset)) OR (

current_state_s9 AND NOT(reset)));

END;