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marta |
-- VHDL data flow description generated from `in_key`
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-- date : Sat Sep 1 20:10:14 2001
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-- Entity Declaration
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ENTITY in_key IS
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PORT (
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clk : in BIT; -- clk
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rst : in BIT; -- rst
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key_sended : in BIT; -- key_sended
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en_bufin : out BIT; -- en_bufin
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req_key : out BIT; -- req_key
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ikey_ready : out BIT; -- ikey_ready
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n_block : out BIT; -- n_block
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vdd : in BIT; -- vdd
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vss : in BIT -- vss
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);
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END in_key;
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-- Architecture Declaration
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ARCHITECTURE VBE OF in_key IS
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SIGNAL current_state : REG_VECTOR(2 DOWNTO 0) REGISTER; -- current_state
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SIGNAL current_state_s7 : BIT; -- current_state_s7
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SIGNAL next_state_s7 : BIT; -- next_state_s7
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SIGNAL current_state_s6 : BIT; -- current_state_s6
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SIGNAL next_state_s6 : BIT; -- next_state_s6
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SIGNAL current_state_s5 : BIT; -- current_state_s5
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SIGNAL next_state_s5 : BIT; -- next_state_s5
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SIGNAL current_state_s4 : BIT; -- current_state_s4
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SIGNAL next_state_s4 : BIT; -- next_state_s4
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SIGNAL current_state_s3 : BIT; -- current_state_s3
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SIGNAL next_state_s3 : BIT; -- next_state_s3
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SIGNAL current_state_s2 : BIT; -- current_state_s2
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SIGNAL next_state_s2 : BIT; -- next_state_s2
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SIGNAL current_state_s1 : BIT; -- current_state_s1
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SIGNAL next_state_s1 : BIT; -- next_state_s1
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SIGNAL current_state_s0 : BIT; -- current_state_s0
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SIGNAL next_state_s0 : BIT; -- next_state_s0
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SIGNAL next_state : BIT_VECTOR(2 DOWNTO 0); -- next_state
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BEGIN
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next_state(0) <= (next_state_s0 OR next_state_s1 OR next_state_s6
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OR next_state_s7);
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next_state(1) <= (next_state_s2 OR next_state_s3 OR next_state_s6
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OR next_state_s7);
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next_state(2) <= (next_state_s1 OR next_state_s3 OR next_state_s5
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OR next_state_s7);
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next_state_s0 <= ((current_state_s0 AND NOT(key_sended)) OR
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current_state_s6);
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current_state_s0 <= (NOT(current_state(2)) AND NOT(current_state(1))
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AND current_state(0));
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next_state_s1 <= (current_state_s0 AND key_sended);
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current_state_s1 <= (current_state(2) AND NOT(current_state(1)) AND
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current_state(0));
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next_state_s2 <= (current_state_s1 OR (current_state_s2 AND NOT(
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key_sended)));
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current_state_s2 <= (NOT(current_state(2)) AND current_state(1) AND
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NOT(current_state(0)));
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next_state_s3 <= (current_state_s2 AND key_sended);
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current_state_s3 <= (current_state(2) AND current_state(1) AND NOT(
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current_state(0)));
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next_state_s4 <= (current_state_s3 OR (current_state_s4 AND NOT(
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key_sended)));
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current_state_s4 <= (NOT(current_state(2)) AND NOT(current_state(1))
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AND NOT(current_state(0)));
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next_state_s5 <= (current_state_s4 AND key_sended);
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current_state_s5 <= (current_state(2) AND NOT(current_state(1)) AND
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NOT(current_state(0)));
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next_state_s6 <= current_state_s5;
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current_state_s6 <= (NOT(current_state(2)) AND current_state(1) AND
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current_state(0));
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next_state_s7 <= '0';
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current_state_s7 <= (current_state(2) AND current_state(1) AND
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current_state(0));
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label0 : BLOCK ((NOT((clk'STABLE)) AND clk) = '1')
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BEGIN
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current_state(0) <= GUARDED (next_state(0) OR rst);
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END BLOCK label0;
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label1 : BLOCK ((NOT((clk'STABLE)) AND clk) = '1')
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BEGIN
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current_state(1) <= GUARDED (next_state(1) AND NOT(rst));
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END BLOCK label1;
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label2 : BLOCK ((NOT((clk'STABLE)) AND clk) = '1')
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BEGIN
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current_state(2) <= GUARDED (next_state(2) AND NOT(rst));
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END BLOCK label2;
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n_block <= NOT(rst OR (current_state_s0 AND NOT(rst)) OR (
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current_state_s6 AND NOT(rst)));
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ikey_ready <= (current_state_s6 AND NOT(rst));
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req_key <= NOT((current_state_s0 AND NOT(rst) AND key_sended
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) OR (current_state_s2 AND NOT(rst) AND key_sended
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) OR (current_state_s4 AND NOT(rst) AND key_sended
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) OR (current_state_s6 AND NOT(rst)));
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en_bufin <= ((current_state_s0 AND NOT(rst) AND key_sended)
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OR (current_state_s2 AND NOT(rst) AND key_sended)
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OR (current_state_s4 AND NOT(rst) AND key_sended));
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END;
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