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marta |
-- VHDL data flow description generated from `mux2to1_bop`
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-- date : Mon Aug 27 06:31:45 2001
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-- Entity Declaration
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ENTITY mux2to1_bop IS
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PORT (
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y : in bit_vector(63 DOWNTO 0) ; -- y
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sel : in BIT; -- sel
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clk : in BIT; -- clk
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rst : in BIT; -- rst
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cp : out bit_vector(31 DOWNTO 0) ; -- cp
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vdd : in BIT; -- vdd
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vss : in BIT -- vss
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);
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END mux2to1_bop;
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-- Architecture Declaration
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ARCHITECTURE behaviour_data_flow OF mux2to1_bop IS
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SIGNAL reg : REG_VECTOR(31 DOWNTO 0) REGISTER; -- reg
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SIGNAL aux12 : BIT; -- aux12
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SIGNAL aux11 : BIT; -- aux11
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BEGIN
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ASSERT ((vdd and not (vss)) = '1')
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REPORT "power supply is missing on mux2to1"
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SEVERITY WARNING;
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aux11 <= (not (sel) and not (rst));
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aux12 <= (not (rst) and sel);
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label0 : BLOCK ((clk and not (clk'STABLE)) = '1')
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BEGIN
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reg (0) <= GUARDED ((not (y (32)) and not (sel)) or not ((not (rst) and (not (sel)
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or y (0)))));
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END BLOCK label0;
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label1 : BLOCK ((clk and not (clk'STABLE)) = '1')
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BEGIN
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reg (1) <= GUARDED ((not (y (33)) and aux11) or (not (y (1)) and aux12));
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END BLOCK label1;
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label2 : BLOCK ((clk and not (clk'STABLE)) = '1')
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BEGIN
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reg (2) <= GUARDED ((not (y (34)) and aux11) or (not (y (2)) and aux12));
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END BLOCK label2;
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label3 : BLOCK ((clk and not (clk'STABLE)) = '1')
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BEGIN
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reg (3) <= GUARDED ((not (y (35)) and aux11) or (not (y (3)) and aux12));
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END BLOCK label3;
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label4 : BLOCK ((clk and not (clk'STABLE)) = '1')
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BEGIN
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reg (4) <= GUARDED ((not (y (36)) and not (sel)) or not ((not (rst) and (not (sel)
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or y (4)))));
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END BLOCK label4;
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label5 : BLOCK ((clk and not (clk'STABLE)) = '1')
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BEGIN
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reg (5) <= GUARDED ((not (y (37)) and aux11) or (not (y (5)) and aux12));
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END BLOCK label5;
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label6 : BLOCK ((clk and not (clk'STABLE)) = '1')
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BEGIN
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reg (6) <= GUARDED ((not (y (38)) and aux11) or (not (y (6)) and aux12));
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END BLOCK label6;
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label7 : BLOCK ((clk and not (clk'STABLE)) = '1')
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BEGIN
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reg (7) <= GUARDED ((not (y (39)) and aux11) or (not (y (7)) and aux12));
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END BLOCK label7;
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label8 : BLOCK ((clk and not (clk'STABLE)) = '1')
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BEGIN
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reg (8) <= GUARDED ((not (y (40)) and not (sel)) or not ((not (rst) and (not (sel)
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or y (8)))));
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END BLOCK label8;
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label9 : BLOCK ((clk and not (clk'STABLE)) = '1')
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BEGIN
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reg (9) <= GUARDED ((not (y (41)) and aux11) or (not (y (9)) and aux12));
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END BLOCK label9;
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label10 : BLOCK ((clk and not (clk'STABLE)) = '1')
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BEGIN
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reg (10) <= GUARDED ((not (y (42)) and aux11) or (not (y (10)) and aux12));
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END BLOCK label10;
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label11 : BLOCK ((clk and not (clk'STABLE)) = '1')
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BEGIN
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reg (11) <= GUARDED ((not (y (43)) and aux11) or (not (y (11)) and aux12));
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END BLOCK label11;
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label12 : BLOCK ((clk and not (clk'STABLE)) = '1')
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BEGIN
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reg (12) <= GUARDED ((not (y (44)) and not (sel)) or not ((not (rst) and (not (sel)
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or y (12)))));
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END BLOCK label12;
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label13 : BLOCK ((clk and not (clk'STABLE)) = '1')
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BEGIN
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reg (13) <= GUARDED ((not (y (45)) and aux11) or (not (y (13)) and aux12));
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END BLOCK label13;
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label14 : BLOCK ((clk and not (clk'STABLE)) = '1')
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BEGIN
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reg (14) <= GUARDED ((not (y (46)) and aux11) or (not (y (14)) and aux12));
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END BLOCK label14;
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label15 : BLOCK ((clk and not (clk'STABLE)) = '1')
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BEGIN
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reg (15) <= GUARDED ((not (y (47)) and aux11) or (not (y (15)) and aux12));
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END BLOCK label15;
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label16 : BLOCK ((clk and not (clk'STABLE)) = '1')
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BEGIN
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reg (16) <= GUARDED ((not (y (48)) and not (sel)) or not ((not (rst) and (not (sel)
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or y (16)))));
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END BLOCK label16;
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label17 : BLOCK ((clk and not (clk'STABLE)) = '1')
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BEGIN
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reg (17) <= GUARDED ((not (y (49)) and aux11) or (not (y (17)) and aux12));
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END BLOCK label17;
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label18 : BLOCK ((clk and not (clk'STABLE)) = '1')
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BEGIN
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reg (18) <= GUARDED ((not (y (50)) and aux11) or (not (y (18)) and aux12));
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END BLOCK label18;
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label19 : BLOCK ((clk and not (clk'STABLE)) = '1')
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BEGIN
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reg (19) <= GUARDED ((not (y (51)) and aux11) or (not (y (19)) and aux12));
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END BLOCK label19;
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label20 : BLOCK ((clk and not (clk'STABLE)) = '1')
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BEGIN
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reg (20) <= GUARDED ((not (y (52)) and not (sel)) or not ((not (rst) and (not (sel)
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or y (20)))));
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END BLOCK label20;
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label21 : BLOCK ((clk and not (clk'STABLE)) = '1')
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BEGIN
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reg (21) <= GUARDED ((not (y (53)) and aux11) or (not (y (21)) and aux12));
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END BLOCK label21;
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label22 : BLOCK ((clk and not (clk'STABLE)) = '1')
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BEGIN
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reg (22) <= GUARDED ((not (y (54)) and aux11) or (not (y (22)) and aux12));
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END BLOCK label22;
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label23 : BLOCK ((clk and not (clk'STABLE)) = '1')
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BEGIN
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reg (23) <= GUARDED ((not (y (55)) and aux11) or (not (y (23)) and aux12));
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END BLOCK label23;
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label24 : BLOCK ((clk and not (clk'STABLE)) = '1')
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BEGIN
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reg (24) <= GUARDED ((not (y (56)) and not (sel)) or not ((not (rst) and (not (sel)
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or y (24)))));
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END BLOCK label24;
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label25 : BLOCK ((clk and not (clk'STABLE)) = '1')
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BEGIN
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reg (25) <= GUARDED ((not (y (57)) and aux11) or (not (y (25)) and aux12));
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END BLOCK label25;
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label26 : BLOCK ((clk and not (clk'STABLE)) = '1')
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BEGIN
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reg (26) <= GUARDED ((not (y (58)) and aux11) or (not (y (26)) and aux12));
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END BLOCK label26;
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label27 : BLOCK ((clk and not (clk'STABLE)) = '1')
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BEGIN
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reg (27) <= GUARDED ((not (y (59)) and aux11) or (not (y (27)) and aux12));
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END BLOCK label27;
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label28 : BLOCK ((clk and not (clk'STABLE)) = '1')
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BEGIN
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reg (28) <= GUARDED ((not (y (60)) and not (sel)) or not ((not (rst) and (not (sel)
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or y (28)))));
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END BLOCK label28;
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label29 : BLOCK ((clk and not (clk'STABLE)) = '1')
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BEGIN
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reg (29) <= GUARDED ((not (y (61)) and aux11) or (not (y (29)) and aux12));
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END BLOCK label29;
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label30 : BLOCK ((clk and not (clk'STABLE)) = '1')
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BEGIN
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reg (30) <= GUARDED ((not (y (62)) and aux11) or (not (y (30)) and aux12));
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END BLOCK label30;
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label31 : BLOCK ((clk and not (clk'STABLE)) = '1')
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BEGIN
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reg (31) <= GUARDED ((not (y (63)) and aux11) or (not (y (31)) and aux12));
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END BLOCK label31;
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cp (0) <= not (reg (0));
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cp (1) <= not (reg (1));
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cp (2) <= not (reg (2));
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cp (3) <= not (reg (3));
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cp (4) <= not (reg (4));
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cp (5) <= not (reg (5));
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cp (6) <= not (reg (6));
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cp (7) <= not (reg (7));
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cp (8) <= not (reg (8));
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cp (9) <= not (reg (9));
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cp (10) <= not (reg (10));
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cp (11) <= not (reg (11));
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cp (12) <= not (reg (12));
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cp (13) <= not (reg (13));
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cp (14) <= not (reg (14));
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cp (15) <= not (reg (15));
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cp (16) <= not (reg (16));
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cp (17) <= not (reg (17));
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cp (18) <= not (reg (18));
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cp (19) <= not (reg (19));
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cp (20) <= not (reg (20));
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cp (21) <= not (reg (21));
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cp (22) <= not (reg (22));
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cp (23) <= not (reg (23));
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cp (24) <= not (reg (24));
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cp (25) <= not (reg (25));
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cp (26) <= not (reg (26));
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cp (27) <= not (reg (27));
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cp (28) <= not (reg (28));
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cp (29) <= not (reg (29));
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cp (30) <= not (reg (30));
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cp (31) <= not (reg (31));
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END;
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