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-- VHDL data flow description generated from `count2x`

--              date : Thu Aug  2 08:33:31 2001

-- Entity Declaration

ENTITY count2x IS

  PORT (

  clk : in BIT; -- clk

  rst : in BIT; -- rst

  q : out bit_vector(1 DOWNTO 0) ;      -- q

  vdd : in BIT; -- vdd

  vss : in BIT  -- vss

  );

END count2x;

-- Architecture Declaration

ARCHITECTURE VBE OF count2x IS

  SIGNAL current_state : REG_VECTOR(1 DOWNTO 0) REGISTER;       -- current_state

  SIGNAL current_state_s3 : BIT;                -- current_state_s3

  SIGNAL next_state_s3 : BIT;           -- next_state_s3

  SIGNAL current_state_s2 : BIT;                -- current_state_s2

  SIGNAL next_state_s2 : BIT;           -- next_state_s2

  SIGNAL current_state_s1 : BIT;                -- current_state_s1

  SIGNAL next_state_s1 : BIT;           -- next_state_s1

  SIGNAL current_state_s0 : BIT;                -- current_state_s0

  SIGNAL next_state_s0 : BIT;           -- next_state_s0

  SIGNAL next_state : BIT_VECTOR(1 DOWNTO 0);   -- next_state

BEGIN

  next_state(0) <= (next_state_s0 OR next_state_s2);

  next_state(1) <= (next_state_s0 OR next_state_s1);

  next_state_s0 <= current_state_s3;

  current_state_s0 <= (current_state(1) AND current_state(0));

  next_state_s1 <= current_state_s0;

  current_state_s1 <= (current_state(1) AND NOT(current_state(0)));

  next_state_s2 <= current_state_s1;

  current_state_s2 <= (NOT(current_state(1)) AND current_state(0));

  next_state_s3 <= current_state_s2;

  current_state_s3 <= (NOT(current_state(1)) AND NOT(current_state(0)));

  label0 : BLOCK ((NOT((clk'STABLE)) AND clk) = '1')

  BEGIN

    current_state(0) <= GUARDED (next_state(0) OR rst);

  END BLOCK label0;

  label1 : BLOCK ((NOT((clk'STABLE)) AND clk) = '1')

  BEGIN

    current_state(1) <= GUARDED (next_state(1) OR rst);

  END BLOCK label1;

q(0) <= ((current_state_s1 AND NOT(rst)) OR (

current_state_s3 AND NOT(rst)));

q(1) <= ((current_state_s2 AND NOT(rst)) OR (

current_state_s3 AND NOT(rst)));

END;