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-- VHDL data flow description generated from `count3x`

--              date : Thu Aug  2 09:52:58 2001

-- Entity Declaration

ENTITY count3x IS

  PORT (

  clk : in BIT; -- clk

  rst : in BIT; -- rst

  q : out bit_vector(2 DOWNTO 0) ;      -- q

  vdd : in BIT; -- vdd

  vss : in BIT  -- vss

  );

END count3x;

-- Architecture Declaration

ARCHITECTURE VBE OF count3x IS

  SIGNAL current_state : REG_VECTOR(2 DOWNTO 0) REGISTER;       -- current_state

  SIGNAL current_state_s7 : BIT;                -- current_state_s7

  SIGNAL next_state_s7 : BIT;           -- next_state_s7

  SIGNAL current_state_s6 : BIT;                -- current_state_s6

  SIGNAL next_state_s6 : BIT;           -- next_state_s6

  SIGNAL current_state_s5 : BIT;                -- current_state_s5

  SIGNAL next_state_s5 : BIT;           -- next_state_s5

  SIGNAL current_state_s4 : BIT;                -- current_state_s4

  SIGNAL next_state_s4 : BIT;           -- next_state_s4

  SIGNAL current_state_s3 : BIT;                -- current_state_s3

  SIGNAL next_state_s3 : BIT;           -- next_state_s3

  SIGNAL current_state_s2 : BIT;                -- current_state_s2

  SIGNAL next_state_s2 : BIT;           -- next_state_s2

  SIGNAL current_state_s1 : BIT;                -- current_state_s1

  SIGNAL next_state_s1 : BIT;           -- next_state_s1

  SIGNAL current_state_s0 : BIT;                -- current_state_s0

  SIGNAL next_state_s0 : BIT;           -- next_state_s0

  SIGNAL next_state : BIT_VECTOR(2 DOWNTO 0);   -- next_state

BEGIN

  next_state(0) <= (next_state_s0 OR next_state_s1 OR next_state_s2

OR next_state_s5);

  next_state(1) <= (next_state_s1 OR next_state_s2 OR next_state_s3

OR next_state_s4);

  next_state(2) <= (next_state_s0 OR next_state_s2 OR next_state_s4

OR next_state_s6);

  next_state_s0 <= current_state_s7;

  current_state_s0 <= (current_state(2) AND NOT(current_state(1)) AND

current_state(0));

  next_state_s1 <= current_state_s0;

  current_state_s1 <= (NOT(current_state(2)) AND current_state(1) AND

current_state(0));

  next_state_s2 <= current_state_s1;

  current_state_s2 <= (current_state(2) AND current_state(1) AND

current_state(0));

  next_state_s3 <= current_state_s2;

  current_state_s3 <= (NOT(current_state(2)) AND current_state(1) AND

NOT(current_state(0)));

  next_state_s4 <= current_state_s3;

  current_state_s4 <= (current_state(2) AND current_state(1) AND NOT(

current_state(0)));

  next_state_s5 <= current_state_s4;

  current_state_s5 <= (NOT(current_state(2)) AND NOT(current_state(1))

AND current_state(0));

  next_state_s6 <= current_state_s5;

  current_state_s6 <= (current_state(2) AND NOT(current_state(1)) AND

NOT(current_state(0)));

  next_state_s7 <= current_state_s6;

  current_state_s7 <= (NOT(current_state(2)) AND NOT(current_state(1))

AND NOT(current_state(0)));

  label0 : BLOCK ((NOT((clk'STABLE)) AND clk) = '1')

  BEGIN

    current_state(0) <= GUARDED (next_state(0) OR rst);

  END BLOCK label0;

  label1 : BLOCK ((NOT((clk'STABLE)) AND clk) = '1')

  BEGIN

    current_state(1) <= GUARDED (next_state(1) AND NOT(rst));

  END BLOCK label1;

  label2 : BLOCK ((NOT((clk'STABLE)) AND clk) = '1')

  BEGIN

    current_state(2) <= GUARDED (next_state(2) OR rst);

  END BLOCK label2;

q(0) <= ((current_state_s1 AND NOT(rst)) OR (

current_state_s3 AND NOT(rst)) OR (current_state_s5 AND NOT(rst))

 OR (current_state_s7 AND NOT(rst)));

q(1) <= ((current_state_s2 AND NOT(rst)) OR (

current_state_s3 AND NOT(rst)) OR (current_state_s6 AND NOT(rst))

 OR (current_state_s7 AND NOT(rst)));

q(2) <= ((current_state_s4 AND NOT(rst)) OR (

current_state_s5 AND NOT(rst)) OR (current_state_s6 AND NOT(rst))

 OR (current_state_s7 AND NOT(rst)));

END;