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[/] [idea/] [trunk/] [behavioral/] [key_regulator/] [count4x.vbe] - Blame information for rev 10

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1 6 marta 
-- VHDL data flow description generated from `count4x`
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--              date : Thu Aug  2 08:55:34 2001
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-- Entity Declaration
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ENTITY count4x IS
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  PORT (
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  clk : in BIT; -- clk
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  rst : in BIT; -- rst
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  q : out bit_vector(3 DOWNTO 0) ;      -- q
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  vdd : in BIT; -- vdd
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  vss : in BIT  -- vss
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  );
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END count4x;
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-- Architecture Declaration
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ARCHITECTURE VBE OF count4x IS
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  SIGNAL current_state : REG_VECTOR(3 DOWNTO 0) REGISTER;       -- current_state
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  SIGNAL current_state_s15 : BIT;               -- current_state_s15
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  SIGNAL next_state_s15 : BIT;          -- next_state_s15
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  SIGNAL current_state_s14 : BIT;               -- current_state_s14
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  SIGNAL next_state_s14 : BIT;          -- next_state_s14
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  SIGNAL current_state_s13 : BIT;               -- current_state_s13
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  SIGNAL next_state_s13 : BIT;          -- next_state_s13
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  SIGNAL current_state_s12 : BIT;               -- current_state_s12
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  SIGNAL next_state_s12 : BIT;          -- next_state_s12
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  SIGNAL current_state_s11 : BIT;               -- current_state_s11
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  SIGNAL next_state_s11 : BIT;          -- next_state_s11
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  SIGNAL current_state_s10 : BIT;               -- current_state_s10
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  SIGNAL next_state_s10 : BIT;          -- next_state_s10
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  SIGNAL current_state_s9 : BIT;                -- current_state_s9
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  SIGNAL next_state_s9 : BIT;           -- next_state_s9
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  SIGNAL current_state_s8 : BIT;                -- current_state_s8
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  SIGNAL next_state_s8 : BIT;           -- next_state_s8
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  SIGNAL current_state_s7 : BIT;                -- current_state_s7
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  SIGNAL next_state_s7 : BIT;           -- next_state_s7
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  SIGNAL current_state_s6 : BIT;                -- current_state_s6
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  SIGNAL next_state_s6 : BIT;           -- next_state_s6
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  SIGNAL current_state_s5 : BIT;                -- current_state_s5
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  SIGNAL next_state_s5 : BIT;           -- next_state_s5
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  SIGNAL current_state_s4 : BIT;                -- current_state_s4
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  SIGNAL next_state_s4 : BIT;           -- next_state_s4
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  SIGNAL current_state_s3 : BIT;                -- current_state_s3
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  SIGNAL next_state_s3 : BIT;           -- next_state_s3
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  SIGNAL current_state_s2 : BIT;                -- current_state_s2
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  SIGNAL next_state_s2 : BIT;           -- next_state_s2
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  SIGNAL current_state_s1 : BIT;                -- current_state_s1
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  SIGNAL next_state_s1 : BIT;           -- next_state_s1
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  SIGNAL current_state_s0 : BIT;                -- current_state_s0
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  SIGNAL next_state_s0 : BIT;           -- next_state_s0
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  SIGNAL next_state : BIT_VECTOR(3 DOWNTO 0);   -- next_state
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BEGIN
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  next_state(0) <= (next_state_s0 OR next_state_s1 OR next_state_s3
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OR next_state_s4 OR next_state_s6 OR next_state_s8
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OR next_state_s12 OR next_state_s14);
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  next_state(1) <= (next_state_s0 OR next_state_s1 OR next_state_s2
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OR next_state_s4 OR next_state_s5 OR next_state_s9
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OR next_state_s12 OR next_state_s13);
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  next_state(2) <= (next_state_s0 OR next_state_s1 OR next_state_s2
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OR next_state_s3 OR next_state_s5 OR next_state_s8
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OR next_state_s10 OR next_state_s11);
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  next_state(3) <= (next_state_s1 OR next_state_s2 OR next_state_s4
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OR next_state_s6 OR next_state_s7 OR next_state_s8
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OR next_state_s9 OR next_state_s10);
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  next_state_s0 <= current_state_s15;
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  current_state_s0 <= (NOT(current_state(3)) AND current_state(2) AND
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current_state(1) AND current_state(0));
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  next_state_s1 <= current_state_s0;
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  current_state_s1 <= (current_state(3) AND current_state(2) AND
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current_state(1) AND current_state(0));
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  next_state_s2 <= current_state_s1;
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  current_state_s2 <= (current_state(3) AND current_state(2) AND
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current_state(1) AND NOT(current_state(0)));
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  next_state_s3 <= current_state_s2;
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  current_state_s3 <= (NOT(current_state(3)) AND current_state(2) AND
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NOT(current_state(1)) AND current_state(0));
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  next_state_s4 <= current_state_s3;
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  current_state_s4 <= (current_state(3) AND NOT(current_state(2)) AND
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current_state(1) AND current_state(0));
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  next_state_s5 <= current_state_s4;
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  current_state_s5 <= (NOT(current_state(3)) AND current_state(2) AND
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current_state(1) AND NOT(current_state(0)));
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  next_state_s6 <= current_state_s5;
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  current_state_s6 <= (current_state(3) AND NOT(current_state(2)) AND
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NOT(current_state(1)) AND current_state(0));
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  next_state_s7 <= current_state_s6;
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  current_state_s7 <= (current_state(3) AND NOT(current_state(2)) AND
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NOT(current_state(1)) AND NOT(current_state(0)));
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  next_state_s8 <= current_state_s7;
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  current_state_s8 <= (current_state(3) AND current_state(2) AND NOT(
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current_state(1)) AND current_state(0));
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  next_state_s9 <= current_state_s8;
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  current_state_s9 <= (current_state(3) AND NOT(current_state(2)) AND
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current_state(1) AND NOT(current_state(0)));
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  next_state_s10 <= current_state_s9;
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  current_state_s10 <= (current_state(3) AND current_state(2) AND NOT(
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current_state(1)) AND NOT(current_state(0)));
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  next_state_s11 <= current_state_s10;
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  current_state_s11 <= (NOT(current_state(3)) AND current_state(2) AND
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NOT(current_state(1)) AND NOT(current_state(0)));
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  next_state_s12 <= current_state_s11;
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  current_state_s12 <= (NOT(current_state(3)) AND NOT(current_state(2))
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AND current_state(1) AND current_state(0));
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  next_state_s13 <= current_state_s12;
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  current_state_s13 <= (NOT(current_state(3)) AND NOT(current_state(2))
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AND current_state(1) AND NOT(current_state(0)));
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  next_state_s14 <= current_state_s13;
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  current_state_s14 <= (NOT(current_state(3)) AND NOT(current_state(2))
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AND NOT(current_state(1)) AND current_state(0));
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  next_state_s15 <= current_state_s14;
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  current_state_s15 <= (NOT(current_state(3)) AND NOT(current_state(2))
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AND NOT(current_state(1)) AND NOT(current_state(0)));
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  label0 : BLOCK ((NOT((clk'STABLE)) AND clk) = '1')
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  BEGIN
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    current_state(0) <= GUARDED (next_state(0) OR rst);
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  END BLOCK label0;
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  label1 : BLOCK ((NOT((clk'STABLE)) AND clk) = '1')
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  BEGIN
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    current_state(1) <= GUARDED (next_state(1) OR rst);
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  END BLOCK label1;
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  label2 : BLOCK ((NOT((clk'STABLE)) AND clk) = '1')
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  BEGIN
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    current_state(2) <= GUARDED (next_state(2) OR rst);
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  END BLOCK label2;
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  label3 : BLOCK ((NOT((clk'STABLE)) AND clk) = '1')
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  BEGIN
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    current_state(3) <= GUARDED (next_state(3) AND NOT(rst));
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  END BLOCK label3;
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q(0) <= ((current_state_s1 AND NOT(rst)) OR (
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current_state_s3 AND NOT(rst)) OR (current_state_s5 AND NOT(rst))
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 OR (current_state_s7 AND NOT(rst)) OR (
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current_state_s9 AND NOT(rst)) OR (current_state_s11 AND NOT(rst)
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) OR (current_state_s13 AND NOT(rst)) OR (
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current_state_s15 AND NOT(rst)));
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q(1) <= ((current_state_s2 AND NOT(rst)) OR (
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current_state_s3 AND NOT(rst)) OR (current_state_s6 AND NOT(rst))
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 OR (current_state_s7 AND NOT(rst)) OR (
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current_state_s10 AND NOT(rst)) OR (current_state_s11 AND NOT(rst)
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) OR (current_state_s14 AND NOT(rst)) OR (
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current_state_s15 AND NOT(rst)));
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q(2) <= ((current_state_s4 AND NOT(rst)) OR (
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current_state_s5 AND NOT(rst)) OR (current_state_s6 AND NOT(rst))
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 OR (current_state_s7 AND NOT(rst)) OR (
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current_state_s12 AND NOT(rst)) OR (current_state_s13 AND NOT(rst)
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) OR (current_state_s14 AND NOT(rst)) OR (
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current_state_s15 AND NOT(rst)));
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q(3) <= ((current_state_s8 AND NOT(rst)) OR (
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current_state_s9 AND NOT(rst)) OR (current_state_s10 AND NOT(rst)
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) OR (current_state_s11 AND NOT(rst)) OR (
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current_state_s12 AND NOT(rst)) OR (current_state_s13 AND NOT(rst)
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) OR (current_state_s14 AND NOT(rst)) OR (
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current_state_s15 AND NOT(rst)));
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END;

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