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-- VHDL data flow description generated from `count5`

--              date : Thu Aug  2 08:47:45 2001

-- Entity Declaration

ENTITY count5 IS

  PORT (

  clk : in BIT; -- clk

  rst : in BIT; -- rst

  q : out bit_vector(4 DOWNTO 0) ;      -- q

  vdd : in BIT; -- vdd

  vss : in BIT  -- vss

  );

END count5;

-- Architecture Declaration

ARCHITECTURE behaviour_data_flow OF count5 IS

  SIGNAL current_state : REG_VECTOR(4 DOWNTO 0) REGISTER;       -- current_state

  SIGNAL aux51 : BIT;           -- aux51

  SIGNAL aux48 : BIT;           -- aux48

  SIGNAL aux46 : BIT;           -- aux46

  SIGNAL aux45 : BIT;           -- aux45

BEGIN

  aux45 <= (current_state (2) and current_state (1));

  aux46 <= (not (current_state (1)) or current_state (2));

  aux48 <= not ((not (current_state (3)) and not (current_state (2))));

  aux51 <= (not (current_state (2)) and current_state (3));

  label0 : BLOCK ((clk and not (clk'STABLE)) = '1')

  BEGIN

    current_state (0) <= GUARDED (rst or (not (current_state (0)) and current_state (3) and not

(current_state (1)) and current_state (2)) or (current_state

(4) and current_state (1) and aux48) or (not (current_state

(4)) and not (current_state (1)) and not ((current_state (3)

xor current_state (2)))) or (current_state (0) and (not (current_state

(3)) or not (current_state (2))) and (current_state (4) or aux45)));

  END BLOCK label0;

  label1 : BLOCK ((clk and not (clk'STABLE)) = '1')

  BEGIN

    current_state (1) <= GUARDED (rst or (current_state (0) and ((not (current_state (1)) and

aux48) or (current_state (4) and not ((not (current_state (3))

or not (current_state (2))))))) or (not (current_state (0))

and (current_state (4) or not ((current_state (3) or current_state

(1))) or aux51) and (not (current_state (4)) or not ((not (current_state

(1)) and (not (current_state (2)) or current_state (3)))))));

  END BLOCK label1;

  label2 : BLOCK ((clk and not (clk'STABLE)) = '1')

  BEGIN

    current_state (2) <= GUARDED (rst or (current_state (4) and not (current_state (3)) and not

(current_state (1)) and current_state (2)) or (not (current_state

(4)) and not ((current_state (1) xor aux48))) or (current_state

(0) and (not ((not (current_state (2)) or current_state (3)))

or (current_state (3) and not ((not (current_state (1)) and

current_state (2)))))));

  END BLOCK label2;

  label3 : BLOCK ((clk and not (clk'STABLE)) = '1')

  BEGIN

    current_state (3) <= GUARDED (rst or (current_state (0) and (not ((not (current_state (3))

or (not (current_state (2)) and not (current_state (1))))) or

not ((current_state (4) or aux45)))) or (not (current_state

(0)) and ((not (current_state (4)) and not (current_state (1))

and not (aux51)) or (current_state (4) and current_state (3)

and aux46))));

  END BLOCK label3;

  label4 : BLOCK ((clk and not (clk'STABLE)) = '1')

  BEGIN

    current_state (4) <= GUARDED (rst or ((not (aux46) or (not (current_state (3)) and not (current_state

(1)) and current_state (2)) or not ((not (current_state (4))

and (current_state (0) or (not (current_state (3)) and current_state

(1)))))) and (not (current_state (4)) or (not (current_state

(0)) and aux45) or (current_state (0) and (aux51 or (not (current_state

(3)) and current_state (1)))))));

  END BLOCK label4;

q (0) <= (not (rst) and ((not (current_state (3)) and not (current_state

(1)) and current_state (2)) or (not (current_state (2)) and

current_state (0) and (current_state (3) or current_state (1)))

or (not (current_state (4)) and (not (current_state (2)) or

(current_state (3) and current_state (1) and current_state (0))))));

q (1) <= (not (rst) and (not (current_state (0)) or current_state (4)

or not (current_state (3)) or (not (current_state (2)) and not

(current_state (1)))) and ((not (current_state (1)) and (not

(current_state (2)) or current_state (3))) or (not (current_state

(4)) and (current_state (3) xor current_state (2)))));

q (2) <= (not (rst) and (not (current_state (0)) or current_state (4)

or aux46) and (not (current_state (3)) or (not (current_state

(0)) and not (current_state (4)) and aux45)));

q (3) <= ((not (rst) and current_state (4) and current_state (0) and current_state

(3) and (current_state (2) xor current_state (1))) or (not (rst)

and (not (current_state (0)) or not (aux48)) and (not (current_state

(2)) or current_state (0) or (current_state (4) and current_state

(1)))));

q (4) <= ((not (rst) and not (current_state (0)) and current_state (4)

and not (aux45)) or (not (rst) and not ((not (current_state

(0)) or current_state (4))) and ((not (current_state (1)) and

current_state (3)) or not (aux46))) or (not (current_state (4))

and not (rst) and not (current_state (0)) and not ((current_state

(3) and (current_state (2) xor current_state (1))))));

END;