1 |
6 |
marta |
-- VHDL data flow description generated from `count5x`
|
2 |
|
|
-- date : Thu Aug 2 08:47:35 2001
|
3 |
|
|
|
4 |
|
|
|
5 |
|
|
-- Entity Declaration
|
6 |
|
|
|
7 |
|
|
ENTITY count5x IS
|
8 |
|
|
PORT (
|
9 |
|
|
clk : in BIT; -- clk
|
10 |
|
|
rst : in BIT; -- rst
|
11 |
|
|
q : out bit_vector(4 DOWNTO 0) ; -- q
|
12 |
|
|
vdd : in BIT; -- vdd
|
13 |
|
|
vss : in BIT -- vss
|
14 |
|
|
);
|
15 |
|
|
END count5x;
|
16 |
|
|
|
17 |
|
|
|
18 |
|
|
-- Architecture Declaration
|
19 |
|
|
|
20 |
|
|
ARCHITECTURE VBE OF count5x IS
|
21 |
|
|
SIGNAL current_state : REG_VECTOR(4 DOWNTO 0) REGISTER; -- current_state
|
22 |
|
|
SIGNAL current_state_s31 : BIT; -- current_state_s31
|
23 |
|
|
SIGNAL next_state_s31 : BIT; -- next_state_s31
|
24 |
|
|
SIGNAL current_state_s30 : BIT; -- current_state_s30
|
25 |
|
|
SIGNAL next_state_s30 : BIT; -- next_state_s30
|
26 |
|
|
SIGNAL current_state_s29 : BIT; -- current_state_s29
|
27 |
|
|
SIGNAL next_state_s29 : BIT; -- next_state_s29
|
28 |
|
|
SIGNAL current_state_s28 : BIT; -- current_state_s28
|
29 |
|
|
SIGNAL next_state_s28 : BIT; -- next_state_s28
|
30 |
|
|
SIGNAL current_state_s27 : BIT; -- current_state_s27
|
31 |
|
|
SIGNAL next_state_s27 : BIT; -- next_state_s27
|
32 |
|
|
SIGNAL current_state_s26 : BIT; -- current_state_s26
|
33 |
|
|
SIGNAL next_state_s26 : BIT; -- next_state_s26
|
34 |
|
|
SIGNAL current_state_s25 : BIT; -- current_state_s25
|
35 |
|
|
SIGNAL next_state_s25 : BIT; -- next_state_s25
|
36 |
|
|
SIGNAL current_state_s24 : BIT; -- current_state_s24
|
37 |
|
|
SIGNAL next_state_s24 : BIT; -- next_state_s24
|
38 |
|
|
SIGNAL current_state_s23 : BIT; -- current_state_s23
|
39 |
|
|
SIGNAL next_state_s23 : BIT; -- next_state_s23
|
40 |
|
|
SIGNAL current_state_s22 : BIT; -- current_state_s22
|
41 |
|
|
SIGNAL next_state_s22 : BIT; -- next_state_s22
|
42 |
|
|
SIGNAL current_state_s21 : BIT; -- current_state_s21
|
43 |
|
|
SIGNAL next_state_s21 : BIT; -- next_state_s21
|
44 |
|
|
SIGNAL current_state_s20 : BIT; -- current_state_s20
|
45 |
|
|
SIGNAL next_state_s20 : BIT; -- next_state_s20
|
46 |
|
|
SIGNAL current_state_s19 : BIT; -- current_state_s19
|
47 |
|
|
SIGNAL next_state_s19 : BIT; -- next_state_s19
|
48 |
|
|
SIGNAL current_state_s18 : BIT; -- current_state_s18
|
49 |
|
|
SIGNAL next_state_s18 : BIT; -- next_state_s18
|
50 |
|
|
SIGNAL current_state_s17 : BIT; -- current_state_s17
|
51 |
|
|
SIGNAL next_state_s17 : BIT; -- next_state_s17
|
52 |
|
|
SIGNAL current_state_s16 : BIT; -- current_state_s16
|
53 |
|
|
SIGNAL next_state_s16 : BIT; -- next_state_s16
|
54 |
|
|
SIGNAL current_state_s15 : BIT; -- current_state_s15
|
55 |
|
|
SIGNAL next_state_s15 : BIT; -- next_state_s15
|
56 |
|
|
SIGNAL current_state_s14 : BIT; -- current_state_s14
|
57 |
|
|
SIGNAL next_state_s14 : BIT; -- next_state_s14
|
58 |
|
|
SIGNAL current_state_s13 : BIT; -- current_state_s13
|
59 |
|
|
SIGNAL next_state_s13 : BIT; -- next_state_s13
|
60 |
|
|
SIGNAL current_state_s12 : BIT; -- current_state_s12
|
61 |
|
|
SIGNAL next_state_s12 : BIT; -- next_state_s12
|
62 |
|
|
SIGNAL current_state_s11 : BIT; -- current_state_s11
|
63 |
|
|
SIGNAL next_state_s11 : BIT; -- next_state_s11
|
64 |
|
|
SIGNAL current_state_s10 : BIT; -- current_state_s10
|
65 |
|
|
SIGNAL next_state_s10 : BIT; -- next_state_s10
|
66 |
|
|
SIGNAL current_state_s9 : BIT; -- current_state_s9
|
67 |
|
|
SIGNAL next_state_s9 : BIT; -- next_state_s9
|
68 |
|
|
SIGNAL current_state_s8 : BIT; -- current_state_s8
|
69 |
|
|
SIGNAL next_state_s8 : BIT; -- next_state_s8
|
70 |
|
|
SIGNAL current_state_s7 : BIT; -- current_state_s7
|
71 |
|
|
SIGNAL next_state_s7 : BIT; -- next_state_s7
|
72 |
|
|
SIGNAL current_state_s6 : BIT; -- current_state_s6
|
73 |
|
|
SIGNAL next_state_s6 : BIT; -- next_state_s6
|
74 |
|
|
SIGNAL current_state_s5 : BIT; -- current_state_s5
|
75 |
|
|
SIGNAL next_state_s5 : BIT; -- next_state_s5
|
76 |
|
|
SIGNAL current_state_s4 : BIT; -- current_state_s4
|
77 |
|
|
SIGNAL next_state_s4 : BIT; -- next_state_s4
|
78 |
|
|
SIGNAL current_state_s3 : BIT; -- current_state_s3
|
79 |
|
|
SIGNAL next_state_s3 : BIT; -- next_state_s3
|
80 |
|
|
SIGNAL current_state_s2 : BIT; -- current_state_s2
|
81 |
|
|
SIGNAL next_state_s2 : BIT; -- next_state_s2
|
82 |
|
|
SIGNAL current_state_s1 : BIT; -- current_state_s1
|
83 |
|
|
SIGNAL next_state_s1 : BIT; -- next_state_s1
|
84 |
|
|
SIGNAL current_state_s0 : BIT; -- current_state_s0
|
85 |
|
|
SIGNAL next_state_s0 : BIT; -- next_state_s0
|
86 |
|
|
SIGNAL next_state : BIT_VECTOR(4 DOWNTO 0); -- next_state
|
87 |
|
|
|
88 |
|
|
BEGIN
|
89 |
|
|
next_state(0) <= (next_state_s0 OR next_state_s1 OR next_state_s3
|
90 |
|
|
OR next_state_s4 OR next_state_s5 OR next_state_s6
|
91 |
|
|
OR next_state_s7 OR next_state_s9 OR next_state_s10
|
92 |
|
|
OR next_state_s13 OR next_state_s14 OR
|
93 |
|
|
next_state_s15 OR next_state_s16 OR next_state_s17 OR
|
94 |
|
|
next_state_s19 OR next_state_s25);
|
95 |
|
|
next_state(1) <= (next_state_s0 OR next_state_s1 OR next_state_s4
|
96 |
|
|
OR next_state_s6 OR next_state_s8 OR next_state_s9
|
97 |
|
|
OR next_state_s11 OR next_state_s12 OR
|
98 |
|
|
next_state_s13 OR next_state_s17 OR next_state_s20 OR
|
99 |
|
|
next_state_s22 OR next_state_s24 OR next_state_s25 OR
|
100 |
|
|
next_state_s28 OR next_state_s29);
|
101 |
|
|
next_state(2) <= (next_state_s0 OR next_state_s1 OR next_state_s2
|
102 |
|
|
OR next_state_s4 OR next_state_s5 OR next_state_s6
|
103 |
|
|
OR next_state_s7 OR next_state_s8 OR next_state_s10
|
104 |
|
|
OR next_state_s12 OR next_state_s16 OR
|
105 |
|
|
next_state_s18 OR next_state_s20 OR next_state_s21 OR
|
106 |
|
|
next_state_s22 OR next_state_s23);
|
107 |
|
|
next_state(3) <= (next_state_s0 OR next_state_s1 OR next_state_s2
|
108 |
|
|
OR next_state_s3 OR next_state_s8 OR next_state_s9
|
109 |
|
|
OR next_state_s10 OR next_state_s11 OR
|
110 |
|
|
next_state_s16 OR next_state_s17 OR next_state_s18 OR
|
111 |
|
|
next_state_s19 OR next_state_s20 OR next_state_s24 OR
|
112 |
|
|
next_state_s26 OR next_state_s27);
|
113 |
|
|
next_state(4) <= (next_state_s0 OR next_state_s3 OR next_state_s4
|
114 |
|
|
OR next_state_s5 OR next_state_s8 OR next_state_s9
|
115 |
|
|
OR next_state_s10 OR next_state_s12 OR
|
116 |
|
|
next_state_s13 OR next_state_s14 OR next_state_s18 OR
|
117 |
|
|
next_state_s21 OR next_state_s24 OR next_state_s26 OR
|
118 |
|
|
next_state_s28 OR next_state_s30);
|
119 |
|
|
next_state_s0 <= current_state_s31;
|
120 |
|
|
current_state_s0 <= (current_state(4) AND current_state(3) AND
|
121 |
|
|
current_state(2) AND current_state(1) AND current_state(0));
|
122 |
|
|
next_state_s1 <= current_state_s0;
|
123 |
|
|
current_state_s1 <= (NOT(current_state(4)) AND current_state(3) AND
|
124 |
|
|
current_state(2) AND current_state(1) AND current_state(0));
|
125 |
|
|
next_state_s2 <= current_state_s1;
|
126 |
|
|
current_state_s2 <= (NOT(current_state(4)) AND current_state(3) AND
|
127 |
|
|
current_state(2) AND NOT(current_state(1)) AND NOT(
|
128 |
|
|
current_state(0)));
|
129 |
|
|
next_state_s3 <= current_state_s2;
|
130 |
|
|
current_state_s3 <= (current_state(4) AND current_state(3) AND NOT(
|
131 |
|
|
current_state(2)) AND NOT(current_state(1)) AND current_state(0));
|
132 |
|
|
next_state_s4 <= current_state_s3;
|
133 |
|
|
current_state_s4 <= (current_state(4) AND NOT(current_state(3)) AND
|
134 |
|
|
current_state(2) AND current_state(1) AND current_state(0));
|
135 |
|
|
next_state_s5 <= current_state_s4;
|
136 |
|
|
current_state_s5 <= (current_state(4) AND NOT(current_state(3)) AND
|
137 |
|
|
current_state(2) AND NOT(current_state(1)) AND current_state(0));
|
138 |
|
|
next_state_s6 <= current_state_s5;
|
139 |
|
|
current_state_s6 <= (NOT(current_state(4)) AND NOT(current_state(3))
|
140 |
|
|
AND current_state(2) AND current_state(1) AND
|
141 |
|
|
current_state(0));
|
142 |
|
|
next_state_s7 <= current_state_s6;
|
143 |
|
|
current_state_s7 <= (NOT(current_state(4)) AND NOT(current_state(3))
|
144 |
|
|
AND current_state(2) AND NOT(current_state(1)) AND
|
145 |
|
|
current_state(0));
|
146 |
|
|
next_state_s8 <= current_state_s7;
|
147 |
|
|
current_state_s8 <= (current_state(4) AND current_state(3) AND
|
148 |
|
|
current_state(2) AND current_state(1) AND NOT(current_state(0)));
|
149 |
|
|
next_state_s9 <= current_state_s8;
|
150 |
|
|
current_state_s9 <= (current_state(4) AND current_state(3) AND NOT(
|
151 |
|
|
current_state(2)) AND current_state(1) AND current_state(0));
|
152 |
|
|
next_state_s10 <= current_state_s9;
|
153 |
|
|
current_state_s10 <= (current_state(4) AND current_state(3) AND
|
154 |
|
|
current_state(2) AND NOT(current_state(1)) AND current_state(0));
|
155 |
|
|
next_state_s11 <= current_state_s10;
|
156 |
|
|
current_state_s11 <= (NOT(current_state(4)) AND current_state(3) AND
|
157 |
|
|
NOT(current_state(2)) AND current_state(1) AND NOT(
|
158 |
|
|
current_state(0)));
|
159 |
|
|
next_state_s12 <= current_state_s11;
|
160 |
|
|
current_state_s12 <= (current_state(4) AND NOT(current_state(3)) AND
|
161 |
|
|
current_state(2) AND current_state(1) AND NOT(current_state(0)));
|
162 |
|
|
next_state_s13 <= current_state_s12;
|
163 |
|
|
current_state_s13 <= (current_state(4) AND NOT(current_state(3)) AND
|
164 |
|
|
NOT(current_state(2)) AND current_state(1) AND
|
165 |
|
|
current_state(0));
|
166 |
|
|
next_state_s14 <= current_state_s13;
|
167 |
|
|
current_state_s14 <= (current_state(4) AND NOT(current_state(3)) AND
|
168 |
|
|
NOT(current_state(2)) AND NOT(current_state(1)) AND
|
169 |
|
|
current_state(0));
|
170 |
|
|
next_state_s15 <= current_state_s14;
|
171 |
|
|
current_state_s15 <= (NOT(current_state(4)) AND NOT(current_state(3))
|
172 |
|
|
AND NOT(current_state(2)) AND NOT(current_state(1))
|
173 |
|
|
AND current_state(0));
|
174 |
|
|
next_state_s16 <= current_state_s15;
|
175 |
|
|
current_state_s16 <= (NOT(current_state(4)) AND current_state(3) AND
|
176 |
|
|
current_state(2) AND NOT(current_state(1)) AND current_state(0));
|
177 |
|
|
next_state_s17 <= current_state_s16;
|
178 |
|
|
current_state_s17 <= (NOT(current_state(4)) AND current_state(3) AND
|
179 |
|
|
NOT(current_state(2)) AND current_state(1) AND
|
180 |
|
|
current_state(0));
|
181 |
|
|
next_state_s18 <= current_state_s17;
|
182 |
|
|
current_state_s18 <= (current_state(4) AND current_state(3) AND
|
183 |
|
|
current_state(2) AND NOT(current_state(1)) AND NOT(
|
184 |
|
|
current_state(0)));
|
185 |
|
|
next_state_s19 <= current_state_s18;
|
186 |
|
|
current_state_s19 <= (NOT(current_state(4)) AND current_state(3) AND
|
187 |
|
|
NOT(current_state(2)) AND NOT(current_state(1)) AND
|
188 |
|
|
current_state(0));
|
189 |
|
|
next_state_s20 <= current_state_s19;
|
190 |
|
|
current_state_s20 <= (NOT(current_state(4)) AND current_state(3) AND
|
191 |
|
|
current_state(2) AND current_state(1) AND NOT(current_state(0)));
|
192 |
|
|
next_state_s21 <= current_state_s20;
|
193 |
|
|
current_state_s21 <= (current_state(4) AND NOT(current_state(3)) AND
|
194 |
|
|
current_state(2) AND NOT(current_state(1)) AND NOT(
|
195 |
|
|
current_state(0)));
|
196 |
|
|
next_state_s22 <= current_state_s21;
|
197 |
|
|
current_state_s22 <= (NOT(current_state(4)) AND NOT(current_state(3))
|
198 |
|
|
AND current_state(2) AND current_state(1) AND NOT(
|
199 |
|
|
current_state(0)));
|
200 |
|
|
next_state_s23 <= current_state_s22;
|
201 |
|
|
current_state_s23 <= (NOT(current_state(4)) AND NOT(current_state(3))
|
202 |
|
|
AND current_state(2) AND NOT(current_state(1)) AND
|
203 |
|
|
NOT(current_state(0)));
|
204 |
|
|
next_state_s24 <= current_state_s23;
|
205 |
|
|
current_state_s24 <= (current_state(4) AND current_state(3) AND NOT(
|
206 |
|
|
current_state(2)) AND current_state(1) AND NOT(current_state(0)));
|
207 |
|
|
next_state_s25 <= current_state_s24;
|
208 |
|
|
current_state_s25 <= (NOT(current_state(4)) AND NOT(current_state(3))
|
209 |
|
|
AND NOT(current_state(2)) AND current_state(1) AND
|
210 |
|
|
current_state(0));
|
211 |
|
|
next_state_s26 <= current_state_s25;
|
212 |
|
|
current_state_s26 <= (current_state(4) AND current_state(3) AND NOT(
|
213 |
|
|
current_state(2)) AND NOT(current_state(1)) AND NOT(
|
214 |
|
|
current_state(0)));
|
215 |
|
|
next_state_s27 <= current_state_s26;
|
216 |
|
|
current_state_s27 <= (NOT(current_state(4)) AND current_state(3) AND
|
217 |
|
|
NOT(current_state(2)) AND NOT(current_state(1)) AND
|
218 |
|
|
NOT(current_state(0)));
|
219 |
|
|
next_state_s28 <= current_state_s27;
|
220 |
|
|
current_state_s28 <= (current_state(4) AND NOT(current_state(3)) AND
|
221 |
|
|
NOT(current_state(2)) AND current_state(1) AND NOT(
|
222 |
|
|
current_state(0)));
|
223 |
|
|
next_state_s29 <= current_state_s28;
|
224 |
|
|
current_state_s29 <= (NOT(current_state(4)) AND NOT(current_state(3))
|
225 |
|
|
AND NOT(current_state(2)) AND current_state(1) AND
|
226 |
|
|
NOT(current_state(0)));
|
227 |
|
|
next_state_s30 <= current_state_s29;
|
228 |
|
|
current_state_s30 <= (current_state(4) AND NOT(current_state(3)) AND
|
229 |
|
|
NOT(current_state(2)) AND NOT(current_state(1)) AND
|
230 |
|
|
NOT(current_state(0)));
|
231 |
|
|
next_state_s31 <= current_state_s30;
|
232 |
|
|
current_state_s31 <= (NOT(current_state(4)) AND NOT(current_state(3))
|
233 |
|
|
AND NOT(current_state(2)) AND NOT(current_state(1))
|
234 |
|
|
AND NOT(current_state(0)));
|
235 |
|
|
label0 : BLOCK ((NOT((clk'STABLE)) AND clk) = '1')
|
236 |
|
|
BEGIN
|
237 |
|
|
current_state(0) <= GUARDED (next_state(0) OR rst);
|
238 |
|
|
END BLOCK label0;
|
239 |
|
|
label1 : BLOCK ((NOT((clk'STABLE)) AND clk) = '1')
|
240 |
|
|
BEGIN
|
241 |
|
|
current_state(1) <= GUARDED (next_state(1) OR rst);
|
242 |
|
|
END BLOCK label1;
|
243 |
|
|
label2 : BLOCK ((NOT((clk'STABLE)) AND clk) = '1')
|
244 |
|
|
BEGIN
|
245 |
|
|
current_state(2) <= GUARDED (next_state(2) OR rst);
|
246 |
|
|
END BLOCK label2;
|
247 |
|
|
label3 : BLOCK ((NOT((clk'STABLE)) AND clk) = '1')
|
248 |
|
|
BEGIN
|
249 |
|
|
current_state(3) <= GUARDED (next_state(3) OR rst);
|
250 |
|
|
END BLOCK label3;
|
251 |
|
|
label4 : BLOCK ((NOT((clk'STABLE)) AND clk) = '1')
|
252 |
|
|
BEGIN
|
253 |
|
|
current_state(4) <= GUARDED (next_state(4) OR rst);
|
254 |
|
|
END BLOCK label4;
|
255 |
|
|
|
256 |
|
|
q(0) <= ((current_state_s1 AND NOT(rst)) OR (
|
257 |
|
|
current_state_s3 AND NOT(rst)) OR (current_state_s5 AND NOT(rst))
|
258 |
|
|
OR (current_state_s7 AND NOT(rst)) OR (
|
259 |
|
|
current_state_s9 AND NOT(rst)) OR (current_state_s11 AND NOT(rst)
|
260 |
|
|
) OR (current_state_s13 AND NOT(rst)) OR (
|
261 |
|
|
current_state_s15 AND NOT(rst)) OR (current_state_s17 AND NOT(rst)
|
262 |
|
|
) OR (current_state_s19 AND NOT(rst)) OR (
|
263 |
|
|
current_state_s21 AND NOT(rst)) OR (current_state_s23 AND NOT(rst)
|
264 |
|
|
) OR (current_state_s25 AND NOT(rst)) OR (
|
265 |
|
|
current_state_s27 AND NOT(rst)) OR (current_state_s29 AND NOT(rst)
|
266 |
|
|
) OR (current_state_s31 AND NOT(rst)));
|
267 |
|
|
|
268 |
|
|
q(1) <= ((current_state_s2 AND NOT(rst)) OR (
|
269 |
|
|
current_state_s3 AND NOT(rst)) OR (current_state_s6 AND NOT(rst))
|
270 |
|
|
OR (current_state_s7 AND NOT(rst)) OR (
|
271 |
|
|
current_state_s10 AND NOT(rst)) OR (current_state_s11 AND NOT(rst)
|
272 |
|
|
) OR (current_state_s14 AND NOT(rst)) OR (
|
273 |
|
|
current_state_s15 AND NOT(rst)) OR (current_state_s18 AND NOT(rst)
|
274 |
|
|
) OR (current_state_s19 AND NOT(rst)) OR (
|
275 |
|
|
current_state_s22 AND NOT(rst)) OR (current_state_s23 AND NOT(rst)
|
276 |
|
|
) OR (current_state_s26 AND NOT(rst)) OR (
|
277 |
|
|
current_state_s27 AND NOT(rst)) OR (current_state_s30 AND NOT(rst)
|
278 |
|
|
) OR (current_state_s31 AND NOT(rst)));
|
279 |
|
|
|
280 |
|
|
q(2) <= ((current_state_s4 AND NOT(rst)) OR (
|
281 |
|
|
current_state_s5 AND NOT(rst)) OR (current_state_s6 AND NOT(rst))
|
282 |
|
|
OR (current_state_s7 AND NOT(rst)) OR (
|
283 |
|
|
current_state_s12 AND NOT(rst)) OR (current_state_s13 AND NOT(rst)
|
284 |
|
|
) OR (current_state_s14 AND NOT(rst)) OR (
|
285 |
|
|
current_state_s15 AND NOT(rst)) OR (current_state_s20 AND NOT(rst)
|
286 |
|
|
) OR (current_state_s21 AND NOT(rst)) OR (
|
287 |
|
|
current_state_s22 AND NOT(rst)) OR (current_state_s23 AND NOT(rst)
|
288 |
|
|
) OR (current_state_s28 AND NOT(rst)) OR (
|
289 |
|
|
current_state_s29 AND NOT(rst)) OR (current_state_s30 AND NOT(rst)
|
290 |
|
|
) OR (current_state_s31 AND NOT(rst)));
|
291 |
|
|
|
292 |
|
|
q(3) <= ((current_state_s8 AND NOT(rst)) OR (
|
293 |
|
|
current_state_s9 AND NOT(rst)) OR (current_state_s10 AND NOT(rst)
|
294 |
|
|
) OR (current_state_s11 AND NOT(rst)) OR (
|
295 |
|
|
current_state_s12 AND NOT(rst)) OR (current_state_s13 AND NOT(rst)
|
296 |
|
|
) OR (current_state_s14 AND NOT(rst)) OR (
|
297 |
|
|
current_state_s15 AND NOT(rst)) OR (current_state_s24 AND NOT(rst)
|
298 |
|
|
) OR (current_state_s25 AND NOT(rst)) OR (
|
299 |
|
|
current_state_s26 AND NOT(rst)) OR (current_state_s27 AND NOT(rst)
|
300 |
|
|
) OR (current_state_s28 AND NOT(rst)) OR (
|
301 |
|
|
current_state_s29 AND NOT(rst)) OR (current_state_s30 AND NOT(rst)
|
302 |
|
|
) OR (current_state_s31 AND NOT(rst)));
|
303 |
|
|
|
304 |
|
|
q(4) <= ((current_state_s16 AND NOT(rst)) OR (
|
305 |
|
|
current_state_s17 AND NOT(rst)) OR (current_state_s18 AND NOT(rst)
|
306 |
|
|
) OR (current_state_s19 AND NOT(rst)) OR (
|
307 |
|
|
current_state_s20 AND NOT(rst)) OR (current_state_s21 AND NOT(rst)
|
308 |
|
|
) OR (current_state_s22 AND NOT(rst)) OR (
|
309 |
|
|
current_state_s23 AND NOT(rst)) OR (current_state_s24 AND NOT(rst)
|
310 |
|
|
) OR (current_state_s25 AND NOT(rst)) OR (
|
311 |
|
|
current_state_s26 AND NOT(rst)) OR (current_state_s27 AND NOT(rst)
|
312 |
|
|
) OR (current_state_s28 AND NOT(rst)) OR (
|
313 |
|
|
current_state_s29 AND NOT(rst)) OR (current_state_s30 AND NOT(rst)
|
314 |
|
|
) OR (current_state_s31 AND NOT(rst)));
|
315 |
|
|
END;
|