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-- VHDL data flow description generated from `ctr_enkey`

--              date : Tue Jul 31 14:21:57 2001

-- Entity Declaration

ENTITY ctr_enkey IS

  PORT (

  clk : in BIT; -- clk

  rst : in BIT; -- rst

  start : in BIT;       -- start

  count : in bit_vector(2 DOWNTO 0) ;   -- count

  en_shft : out BIT;    -- en_shft

  en_count : out BIT;   -- en_count

  sel1 : out BIT;       -- sel1

  sel2 : out BIT;       -- sel2

  c_count : out BIT;    -- c_count

  finish : out BIT;     -- finish

  en_out : out BIT;     -- en_out

  vdd : in BIT; -- vdd

  vss : in BIT  -- vss

  );

END ctr_enkey;

-- Architecture Declaration

ARCHITECTURE behaviour_data_flow OF ctr_enkey IS

  SIGNAL current_state : REG_VECTOR(3 DOWNTO 0) REGISTER;       -- current_state

  SIGNAL aux44 : BIT;           -- aux44

  SIGNAL aux38 : BIT;           -- aux38

  SIGNAL aux35 : BIT;           -- aux35

  SIGNAL aux33 : BIT;           -- aux33

  SIGNAL aux32 : BIT;           -- aux32

  SIGNAL auxinit1 : BIT;                -- auxinit1

  SIGNAL aux40 : BIT;           -- aux40

  SIGNAL aux41 : BIT;           -- aux41

BEGIN

  aux41 <= (not (current_state (3)) or current_state (2));

  aux40 <= (not (count (2)) and not (count (1)) and start and count (0));

  auxinit1 <= (not (rst) and not ((current_state (0) and not (current_state

(1)) and not (current_state (3)))) and ((not (count (2)) and

not (count (1)) and start) or not ((current_state (3) and not

((current_state (2) or current_state (0)))))));

  aux32 <= (not (count (0)) and current_state (3) and not (count (2)) and

not (count (1)) and start);

  aux33 <= (not (current_state (3)) and current_state (1));

  aux35 <= (start and count (2) and count (1) and count (0));

  aux38 <= (current_state (2) or current_state (1));

  aux44 <= not ((not (current_state (1)) and (not (current_state (3)) or

start)));

  label0 : BLOCK ((not (clk) and not (clk'STABLE)) = '1')

  BEGIN

    current_state (0) <= GUARDED (not (rst) and (not (current_state (0)) or current_state (2)

or not (aux33)) and (not (current_state (3)) or current_state

(0) or aux38 or aux35));

  END BLOCK label0;

  label1 : BLOCK ((not (clk) and not (clk'STABLE)) = '1')

  BEGIN

    current_state (1) <= GUARDED (not (rst) and (not (current_state (0)) or current_state (1)

or not (aux41)) and (current_state (3) or current_state (0)

or not (aux38)) and (not (current_state (3)) or current_state

(0) or aux38 or aux40));

  END BLOCK label1;

  label2 : BLOCK ((not (clk) and not (clk'STABLE)) = '1')

  BEGIN

    current_state (2) <= GUARDED (not (rst) and ((current_state (0) and aux33) or (current_state

(2) and not (aux33)) or (not (current_state (0)) and aux32)));

  END BLOCK label2;

  label3 : BLOCK ((not (clk) and not (clk'STABLE)) = '1')

  BEGIN

    current_state (3) <= GUARDED (rst or current_state (2) or (current_state (3) and current_state

(0)) or aux44);

  END BLOCK label3;

en_out <= (not (rst) and (aux33 or (not ((current_state (2) or current_state

(0))) and aux32)));

finish <= (not (rst) and ((current_state (0) and not (current_state (1))

and not (current_state (3))) or (current_state (3) and not ((current_state

(2) or current_state (0))) and aux35)));

c_count <= (not (rst) and ((current_state (3) and current_state (0)) or

(not (current_state (0)) and current_state (2) and not (aux33))));

sel2 <= auxinit1;

sel1 <= '0';

en_count <= auxinit1;

en_shft <= (not (rst) and not ((current_state (2) or current_state (0)))

and ((not (current_state (1)) and not (current_state (3))) or

(current_state (3) and aux40)));

END;