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-- VHDL data flow description generated from `komp1`

--              date : Mon Jul 30 21:22:25 2001

-- Entity Declaration

ENTITY komp1 IS

  PORT (

  kin : in bit_vector(15 DOWNTO 0) ;    -- kin

  kout : out bit_vector(16 DOWNTO 0) ;  -- kout

  vdd : in BIT; -- vdd

  vss : in BIT  -- vss

  );

END komp1;

-- Architecture Declaration

ARCHITECTURE behaviour_data_flow OF komp1 IS

BEGIN

  ASSERT ((vdd and not (vss)) = '1')

    REPORT "power supply is missing on komp1x"

    SEVERITY WARNING;

kout (0) <= kin (0);

kout (1) <= kin (1);

kout (2) <= kin (2);

kout (3) <= kin (3);

kout (4) <= kin (4);

kout (5) <= kin (5);

kout (6) <= kin (6);

kout (7) <= kin (7);

kout (8) <= kin (8);

kout (9) <= kin (9);

kout (10) <= kin (10);

kout (11) <= kin (11);

kout (12) <= kin (12);

kout (13) <= kin (13);

kout (14) <= kin (14);

kout (15) <= kin (15);

kout (16) <= (not (kin (15)) and not (kin (14)) and not (kin (13)) and not

(kin (12)) and not (kin (11)) and not (kin (10)) and not (kin

(9)) and not (kin (8)) and not (kin (7)) and not (kin (6)) and

not (kin (5)) and not (kin (4)) and not (kin (3)) and not (kin

(2)) and not (kin (1)) and not (kin (0)));

END;