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-- VHDL data flow description generated from `kontrol_kunci`

--              date : Sat Jul 28 17:00:56 2001

-- Entity Declaration

ENTITY kontrol_kunci IS

  PORT (

  clk : in BIT; -- clk

  start : in BIT;       -- start

  rst : in BIT; -- rst

  f_enkey : in BIT;     -- f_enkey

  f_invmul : in BIT;    -- f_invmul

  f_invadd : in BIT;    -- f_invadd

  rst_all : out BIT;    -- rst_all

  key_ready : out BIT;  -- key_ready

  s_enkey : out BIT;    -- s_enkey

  s_invmul : out BIT;   -- s_invmul

  s_invadd : out BIT;   -- s_invadd

  vdd : in BIT; -- vdd

  vss : in BIT  -- vss

  );

END kontrol_kunci;

-- Architecture Declaration

ARCHITECTURE behaviour_data_flow OF kontrol_kunci IS

  SIGNAL current_state : REG_VECTOR(3 DOWNTO 0) REGISTER;       -- current_state

  SIGNAL aux23 : BIT;           -- aux23

  SIGNAL aux19 : BIT;           -- aux19

BEGIN

  aux19 <= (current_state (3) or current_state (0));

  aux23 <= (current_state (1) and current_state (0));

  label0 : BLOCK ((not (clk) and not (clk'STABLE)) = '1')

  BEGIN

    current_state (0) <= GUARDED (not (rst) and (not (current_state (2)) or (not (current_state

(1)) and current_state (3)) or aux23) and (not (current_state

(1)) or (not (f_enkey) and start) or not ((not (current_state

(2)) and not (current_state (3))))) and (not ((not (current_state

(2)) and not (current_state (1)))) or (f_invmul and not (aux19))));

  END BLOCK label0;

  label1 : BLOCK ((not (clk) and not (clk'STABLE)) = '1')

  BEGIN

    current_state (1) <= GUARDED (rst or (not (current_state (2)) and not (current_state (1))

and not (current_state (3))) or (not (f_invadd) and aux23) or

(not (current_state (2)) and current_state (1) and (not (start)

or aux19)));

  END BLOCK label1;

  label2 : BLOCK ((not (clk) and not (clk'STABLE)) = '1')

  BEGIN

    current_state (2) <= GUARDED (not (rst) and (current_state (2) or not (aux19)) and (not (current_state

(1)) or (f_invadd and aux19)));

  END BLOCK label2;

  label3 : BLOCK ((not (clk) and not (clk'STABLE)) = '1')

  BEGIN

    current_state (3) <= GUARDED (not (rst) and ((current_state (2) and aux23) or (current_state

(3) and not ((f_invadd and current_state (1)))) or (not (current_state

(2)) and ((current_state (3) and current_state (1)) or (not

(current_state (1)) and not (current_state (0)))))));

  END BLOCK label3;

s_invadd <= (not (rst) and ((not (current_state (2)) and current_state (3))

or (not (f_invadd) and current_state (2) and (not (current_state

(0)) or current_state (1)) and aux19)));

s_invmul <= (not (rst) and ((current_state (2) and ((not (current_state (0))

and current_state (3)) or (not (current_state (1)) and not (current_state

(3))))) or (not (current_state (2)) and not (current_state (1))

and not ((not (current_state (3)) and (f_invmul or current_state

(0)))))));

s_enkey <= (not (rst) and not (current_state (2)) and not (f_enkey) and

not (current_state (3)) and start and current_state (1));

key_ready <= (not (rst) and current_state (2) and ((not (current_state (1))

and current_state (3)) or (current_state (0) and f_invadd and

current_state (1))));

rst_all <= (rst or (not (current_state (2)) and not (current_state (3))

and (current_state (0) or (not (start) and current_state (1)))));

END;