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-- VHDL data flow description generated from `kontrol_utama_invadd`

--              date : Sun Jul 29 23:45:28 2001

-- Entity Declaration

ENTITY kontrol_utama_invadd IS

  PORT (

  clk : in BIT; -- clk

  rst : in BIT; -- rst

  start : in BIT;       -- start

  n_dtin : in bit_vector(4 DOWNTO 0) ;  -- n_dtin

  n_dtout : in bit_vector(4 DOWNTO 0) ; -- n_dtout

  c_cdtin : out BIT;    -- c_cdtin

  en_cdtin : out BIT;   -- en_cdtin

  c_cdtout : out BIT;   -- c_cdtout

  en_cdtout : out BIT;  -- en_cdtout

  en_out : out BIT;     -- en_out

  en_in : out BIT;      -- en_in

  finish : out BIT;     -- finish

  vdd : in BIT; -- vdd

  vss : in BIT  -- vss

  );

END kontrol_utama_invadd;

-- Architecture Declaration

ARCHITECTURE behaviour_data_flow OF kontrol_utama_invadd IS

  SIGNAL current_state : REG_VECTOR(2 DOWNTO 0) REGISTER;       -- current_state

  SIGNAL aux27 : BIT;           -- aux27

  SIGNAL aux25 : BIT;           -- aux25

  SIGNAL aux21 : BIT;           -- aux21

  SIGNAL aux20 : BIT;           -- aux20

  SIGNAL auxinit1 : BIT;                -- auxinit1

  SIGNAL auxinit2 : BIT;                -- auxinit2

  SIGNAL aux29 : BIT;           -- aux29

  SIGNAL aux30 : BIT;           -- aux30

BEGIN

  aux30 <= (not (rst) and start and aux29 and aux20);

  aux29 <= (not (current_state (1)) and current_state (2));

  auxinit2 <= ((not (current_state (2)) and not (current_state (1)) and not

(rst)) or aux27);

  auxinit1 <= (not (rst) and not ((current_state (2) xor current_state (1))));

  aux20 <= not ((not (n_dtout (3)) and not (n_dtout (2)) and not (n_dtout

(0)) and n_dtout (4) and n_dtout (1)));

  aux21 <= (not (rst) and start and not (aux20));

  aux25 <= (n_dtin (4) or n_dtin (3) or n_dtin (2) or n_dtin (1) or n_dtin

(0));

  aux27 <= (not (rst) and current_state (2) and (current_state (1) or (start

and not (aux25) and aux20)));

  label0 : BLOCK ((not (clk) and not (clk'STABLE)) = '1')

  BEGIN

    current_state (0) <= GUARDED ((not (current_state (2)) and not (rst) and (not (current_state

(1)) or current_state (0))) or aux27);

  END BLOCK label0;

  label1 : BLOCK ((not (clk) and not (clk'STABLE)) = '1')

  BEGIN

    current_state (1) <= GUARDED ((not (rst) and not (aux29)) or aux21);

  END BLOCK label1;

  label2 : BLOCK ((not (clk) and not (clk'STABLE)) = '1')

  BEGIN

    current_state (2) <= GUARDED (rst or (current_state (1) and current_state (0)) or (not (start)

and not (current_state (1))) or not ((current_state (2) xor

current_state (1))));

  END BLOCK label2;

finish <= ((not (current_state (2)) and not (rst) and current_state (1))

or (aux29 and aux21));

en_in <= aux30;

en_out <= auxinit1;

en_cdtout <= auxinit2;

c_cdtout <= (aux25 and aux30);

en_cdtin <= auxinit2;

c_cdtin <= auxinit1;

END;