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-- VHDL data flow description generated from `kontrol_utama_invaddx`
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-- date : Sun Jul 29 23:45:16 2001
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-- Entity Declaration
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ENTITY kontrol_utama_invaddx IS
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PORT (
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clk : in BIT; -- clk
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rst : in BIT; -- rst
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start : in BIT; -- start
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n_dtin : in bit_vector(4 DOWNTO 0) ; -- n_dtin
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n_dtout : in bit_vector(4 DOWNTO 0) ; -- n_dtout
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c_cdtin : out BIT; -- c_cdtin
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en_cdtin : out BIT; -- en_cdtin
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c_cdtout : out BIT; -- c_cdtout
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en_cdtout : out BIT; -- en_cdtout
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en_out : out BIT; -- en_out
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en_in : out BIT; -- en_in
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finish : out BIT; -- finish
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vdd : in BIT; -- vdd
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vss : in BIT -- vss
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);
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END kontrol_utama_invaddx;
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-- Architecture Declaration
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ARCHITECTURE VBE OF kontrol_utama_invaddx IS
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SIGNAL current_state : REG_VECTOR(2 DOWNTO 0) REGISTER; -- current_state
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SIGNAL current_state_s4 : BIT; -- current_state_s4
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SIGNAL next_state_s4 : BIT; -- next_state_s4
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SIGNAL current_state_s3 : BIT; -- current_state_s3
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SIGNAL next_state_s3 : BIT; -- next_state_s3
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SIGNAL current_state_s2 : BIT; -- current_state_s2
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SIGNAL next_state_s2 : BIT; -- next_state_s2
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SIGNAL current_state_s1 : BIT; -- current_state_s1
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SIGNAL next_state_s1 : BIT; -- next_state_s1
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SIGNAL current_state_s0 : BIT; -- current_state_s0
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SIGNAL next_state_s0 : BIT; -- next_state_s0
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SIGNAL next_state : BIT_VECTOR(2 DOWNTO 0); -- next_state
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BEGIN
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next_state(0) <= (next_state_s1 OR next_state_s3);
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next_state(1) <= (next_state_s3 OR next_state_s4);
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next_state(2) <= (next_state_s0 OR next_state_s3);
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next_state_s0 <= (current_state_s0 AND NOT(start));
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current_state_s0 <= (current_state(2) AND NOT(current_state(1)));
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next_state_s1 <= (current_state_s0 AND (n_dtout(0) OR NOT(
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n_dtout(1)) OR n_dtout(2) OR n_dtout(3) OR NOT(n_dtout(4)))
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AND NOT(n_dtin(0)) AND NOT(n_dtin(1)) AND NOT(
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n_dtin(2)) AND NOT(n_dtin(3)) AND NOT(n_dtin(4)) AND start
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);
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current_state_s1 <= (NOT(current_state(2)) AND current_state(0));
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next_state_s2 <= (current_state_s0 AND (n_dtout(0) OR NOT(
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n_dtout(1)) OR n_dtout(2) OR n_dtout(3) OR NOT(n_dtout(4)))
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AND (n_dtin(0) OR n_dtin(1) OR n_dtin(2) OR
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n_dtin(3) OR n_dtin(4)) AND start);
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current_state_s2 <= (NOT(current_state(2)) AND NOT(current_state(1))
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AND NOT(current_state(0)));
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next_state_s3 <= (current_state_s1 OR current_state_s2 OR
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current_state_s3);
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current_state_s3 <= (current_state(2) AND current_state(1));
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next_state_s4 <= ((current_state_s0 AND NOT(n_dtout(0)) AND
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n_dtout(1) AND NOT(n_dtout(2)) AND NOT(n_dtout(3)) AND
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n_dtout(4) AND start) OR current_state_s4);
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current_state_s4 <= (NOT(current_state(2)) AND current_state(1));
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label0 : BLOCK ((NOT((clk'STABLE)) AND NOT(clk)) = '1')
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BEGIN
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current_state(0) <= GUARDED (next_state(0) AND NOT(rst));
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END BLOCK label0;
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label1 : BLOCK ((NOT((clk'STABLE)) AND NOT(clk)) = '1')
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BEGIN
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current_state(1) <= GUARDED (next_state(1) AND NOT(rst));
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END BLOCK label1;
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label2 : BLOCK ((NOT((clk'STABLE)) AND NOT(clk)) = '1')
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BEGIN
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current_state(2) <= GUARDED (next_state(2) OR rst);
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END BLOCK label2;
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finish <= ((current_state_s0 AND NOT(n_dtout(0)) AND
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n_dtout(1) AND NOT(n_dtout(2)) AND NOT(n_dtout(3)) AND
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n_dtout(4) AND NOT(rst) AND start) OR (current_state_s4 AND
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NOT(rst)));
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en_in <= (current_state_s0 AND (n_dtout(0) OR NOT(
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n_dtout(1)) OR n_dtout(2) OR n_dtout(3) OR NOT(n_dtout(4)))
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AND NOT(rst) AND start);
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en_out <= NOT(rst OR (current_state_s0 AND NOT(rst)) OR (
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current_state_s4 AND NOT(rst)));
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en_cdtout <= NOT(rst OR (current_state_s0 AND ((NOT(rst) AND
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NOT(start)) OR (((NOT(n_dtout(0)) AND n_dtout(1) AND
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NOT(n_dtout(2)) AND NOT(n_dtout(3)) AND
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n_dtout(4)) OR n_dtin(0) OR n_dtin(1) OR n_dtin(2) OR
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n_dtin(3) OR n_dtin(4)) AND NOT(rst)))) OR (
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current_state_s4 AND NOT(rst)));
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c_cdtout <= (current_state_s0 AND (n_dtout(0) OR NOT(
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n_dtout(1)) OR n_dtout(2) OR n_dtout(3) OR NOT(n_dtout(4)))
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AND (n_dtin(0) OR n_dtin(1) OR n_dtin(2) OR
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n_dtin(3) OR n_dtin(4)) AND NOT(rst) AND start);
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en_cdtin <= NOT(rst OR (current_state_s0 AND ((NOT(rst) AND
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NOT(start)) OR (((NOT(n_dtout(0)) AND n_dtout(1) AND
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NOT(n_dtout(2)) AND NOT(n_dtout(3)) AND
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n_dtout(4)) OR n_dtin(0) OR n_dtin(1) OR n_dtin(2) OR
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n_dtin(3) OR n_dtin(4)) AND NOT(rst)))) OR (
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current_state_s4 AND NOT(rst)));
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c_cdtin <= NOT(rst OR (current_state_s0 AND NOT(rst)) OR (
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current_state_s4 AND NOT(rst)));
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END;
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