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--Nama file : mux12to6x.vbe

--Deskripsi : mux 12 to 6 16 bit

--Author    : Mas Adit

--Tanggal  : 27 Agustus 2001

entity mux12to6x is

port (

         i1 : in bit_vector(15 downto 0);

        i2 : in bit_vector(15 downto 0);

        i3 : in bit_vector(15 downto 0);

        i4 : in bit_vector(15 downto 0);

        i5 : in bit_vector(15 downto 0);

        i6 : in bit_vector(15 downto 0);

        i7 : in bit_vector(15 downto 0);

        i8 : in bit_vector(15 downto 0);

        i9 : in bit_vector(15 downto 0);

        i10 : in bit_vector(15 downto 0);

        i11 : in bit_vector(15 downto 0);

        i12 : in bit_vector(15 downto 0);

        en  : in bit;

        clr  : in bit;

        sel  : in bit;

        o1 : out bit_vector(15 downto 0);

        o2 : out bit_vector(15 downto 0);

        o3 : out bit_vector(15 downto 0);

        o4 : out bit_vector(15 downto 0);

        o5 : out bit_vector(15 downto 0);

        o6 : out bit_vector(15 downto 0);

        vdd : in bit;

        vss : in bit

);

end mux12to6x;

architecture vbe of mux12to6x is

constant nol : bit_vector(15 downto 0) := "0000000000000000";

signal temp1 : bit_vector(15 downto 0);

signal temp2 : bit_vector(15 downto 0);

signal temp3 : bit_vector(15 downto 0);

signal temp4 : bit_vector(15 downto 0);

signal temp5 : bit_vector(15 downto 0);

signal temp6 : bit_vector(15 downto 0);

signal tempx1 : bit_vector(15 downto 0);

signal tempx2 : bit_vector(15 downto 0);

signal tempx3 : bit_vector(15 downto 0);

signal tempx4 : bit_vector(15 downto 0);

signal tempx5 : bit_vector(15 downto 0);

signal tempx6 : bit_vector(15 downto 0);

signal reg1 : reg_vector(15 downto 0) register;

signal reg2 : reg_vector(15 downto 0) register;

signal reg3 : reg_vector(15 downto 0) register;

signal reg4 : reg_vector(15 downto 0) register;

signal reg5 : reg_vector(15 downto 0) register;

signal reg6 : reg_vector(15 downto 0) register;

begin

--proses o1

with sel select

temp1 <= i1 when '1',

              i7 when '0',

              nol when others;

flip_flop1 : block ((en = '1') and not(en'STABLE))

begin

        reg1 <= guarded temp1;

end block;

tempx1 <= nol when (clr = '1')

               else reg1;

o1 <= tempx1;

--proses o2

with sel select

temp2 <= i2 when '1',

              i9 when '0',

              nol when others;

flip_flop2 : block ((en = '1') and not(en'STABLE))

begin

        reg2 <= guarded temp2;

end block;

tempx2 <= nol when (clr = '1')

               else reg2;

o2 <= tempx2;

--proses o3

with sel select

temp3 <= i3 when '1',

              i9 when '0',

              nol when others;

flip_flop3 : block ((en = '1') and not(en'STABLE))

begin

        reg3 <= guarded temp3;

end block;

tempx3 <= nol when (clr = '1')

               else reg3;

o3 <= tempx3;

--proses o4

with sel select

temp4 <= i4 when '1',

              i10 when '0',

              nol when others;

flip_flop4 : block ((en = '1') and not(en'STABLE))

begin

        reg4 <= guarded temp4;

end block;

tempx4 <= nol when (clr = '1')

               else reg4;

o4 <= tempx4;

--proses o5

with sel select

temp5 <= i5 when '1',

              i11 when '0',

              nol when others;

flip_flop5 : block ((en = '1') and not(en'STABLE))

begin

        reg5 <= guarded temp5;

end block;

tempx5 <= nol when (clr = '1')

               else reg5;

o5 <= tempx5;

--proses o6

with sel select

temp6 <= i6 when '1',

              i12 when '0',

              nol when others;

flip_flop6 : block ((en = '1') and not(en'STABLE))

begin

        reg6 <= guarded temp6;

end block;

tempx6 <= nol when (clr = '1')

               else reg6;

o6 <= tempx6;

--check power supply

assert ((vdd = '1') and (vss = '0'))

report "power supply is missing on mux12to6x"

severity warning;

end vbe;