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[/] [idea/] [trunk/] [behavioral/] [key_regulator/] [reg16.vbe] - Blame information for rev 9

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1 6 marta 
-- VHDL data flow description generated from `reg16`
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--              date : Tue Jul 31 11:00:32 2001
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-- Entity Declaration
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ENTITY reg16 IS
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  PORT (
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  a : in bit_vector(15 DOWNTO 0) ;      -- a
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  en : in BIT;  -- en
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  clr : in BIT; -- clr
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  b : out bit_vector(15 DOWNTO 0) ;     -- b
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  vdd : in BIT; -- vdd
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  vss : in BIT  -- vss
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  );
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END reg16;
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-- Architecture Declaration
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ARCHITECTURE behaviour_data_flow OF reg16 IS
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  SIGNAL reg : REG_VECTOR(15 DOWNTO 0) REGISTER;        -- reg
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BEGIN
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  ASSERT ((vdd and not (vss)) = '1')
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    REPORT "power supply is missing on reg15x"
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    SEVERITY WARNING;
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  label0 : BLOCK ((en and not (en'STABLE)) = '1')
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  BEGIN
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    reg (0) <= GUARDED a (0);
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  END BLOCK label0;
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  label1 : BLOCK ((en and not (en'STABLE)) = '1')
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  BEGIN
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    reg (1) <= GUARDED a (1);
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  END BLOCK label1;
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  label2 : BLOCK ((en and not (en'STABLE)) = '1')
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  BEGIN
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    reg (2) <= GUARDED a (2);
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  END BLOCK label2;
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  label3 : BLOCK ((en and not (en'STABLE)) = '1')
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  BEGIN
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    reg (3) <= GUARDED a (3);
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  END BLOCK label3;
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  label4 : BLOCK ((en and not (en'STABLE)) = '1')
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  BEGIN
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    reg (4) <= GUARDED a (4);
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  END BLOCK label4;
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  label5 : BLOCK ((en and not (en'STABLE)) = '1')
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  BEGIN
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    reg (5) <= GUARDED a (5);
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  END BLOCK label5;
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  label6 : BLOCK ((en and not (en'STABLE)) = '1')
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  BEGIN
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    reg (6) <= GUARDED a (6);
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  END BLOCK label6;
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  label7 : BLOCK ((en and not (en'STABLE)) = '1')
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  BEGIN
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    reg (7) <= GUARDED a (7);
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  END BLOCK label7;
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  label8 : BLOCK ((en and not (en'STABLE)) = '1')
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  BEGIN
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    reg (8) <= GUARDED a (8);
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  END BLOCK label8;
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  label9 : BLOCK ((en and not (en'STABLE)) = '1')
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  BEGIN
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    reg (9) <= GUARDED a (9);
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  END BLOCK label9;
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  label10 : BLOCK ((en and not (en'STABLE)) = '1')
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  BEGIN
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    reg (10) <= GUARDED a (10);
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  END BLOCK label10;
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  label11 : BLOCK ((en and not (en'STABLE)) = '1')
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  BEGIN
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    reg (11) <= GUARDED a (11);
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  END BLOCK label11;
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  label12 : BLOCK ((en and not (en'STABLE)) = '1')
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  BEGIN
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    reg (12) <= GUARDED a (12);
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  END BLOCK label12;
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  label13 : BLOCK ((en and not (en'STABLE)) = '1')
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  BEGIN
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    reg (13) <= GUARDED a (13);
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  END BLOCK label13;
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  label14 : BLOCK ((en and not (en'STABLE)) = '1')
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  BEGIN
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    reg (14) <= GUARDED a (14);
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  END BLOCK label14;
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  label15 : BLOCK ((en and not (en'STABLE)) = '1')
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  BEGIN
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    reg (15) <= GUARDED a (15);
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  END BLOCK label15;
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b (0) <= (not (clr) and reg (0));
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b (1) <= (not (clr) and reg (1));
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b (2) <= (not (clr) and reg (2));
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b (3) <= (not (clr) and reg (3));
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b (4) <= (not (clr) and reg (4));
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b (5) <= (not (clr) and reg (5));
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b (6) <= (not (clr) and reg (6));
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b (7) <= (not (clr) and reg (7));
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b (8) <= (not (clr) and reg (8));
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b (9) <= (not (clr) and reg (9));
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b (10) <= (not (clr) and reg (10));
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b (11) <= (not (clr) and reg (11));
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b (12) <= (not (clr) and reg (12));
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b (13) <= (not (clr) and reg (13));
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b (14) <= (not (clr) and reg (14));
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b (15) <= (not (clr) and reg (15));
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END;

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