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-- VHDL data flow description generated from `zero1`

--              date : Mon Jul 30 17:44:24 2001

-- Entity Declaration

ENTITY zero1 IS

  PORT (

  a : out BIT;  -- a

  vdd : in BIT; -- vdd

  vss : in BIT  -- vss

  );

END zero1;

-- Architecture Declaration

ARCHITECTURE behaviour_data_flow OF zero1 IS

BEGIN

  ASSERT ((vdd and not (vss)) = '1')

    REPORT "power supply is missing on zero1x"

    SEVERITY WARNING;

a <= '0';

END;