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[/] [idea/] [trunk/] [behavioral/] [main control/] [cfb.vbe] - Blame information for rev 10

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1 6 marta 
-- VHDL data flow description generated from `cfb`
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--              date : Sat Sep  1 20:21:49 2001
3 
 
4 
 
5 
-- Entity Declaration
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7 
ENTITY cfb IS
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  PORT (
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  active : in BIT;      -- active
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  clk : in BIT; -- clk
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  key_ready : in BIT;   -- key_ready
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  dt_ready : in BIT;    -- dt_ready
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  finish : in BIT;      -- finish
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  e : in BIT;   -- e
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  first_dt : inout BIT; -- first_dt
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  e_mesin : out BIT;    -- e_mesin
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  s_mesin : out BIT;    -- s_mesin
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  s_gen_key : out BIT;  -- s_gen_key
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  emp_buf : out BIT;    -- emp_buf
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  cp_ready : out BIT;   -- cp_ready
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  cke_b_mode : out BIT; -- cke_b_mode
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  en_in : out BIT;      -- en_in
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  en_iv : out BIT;      -- en_iv
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  en_rcbc : out BIT;    -- en_rcbc
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  en_out : out BIT;     -- en_out
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  sel1 : out bit_vector(1 DOWNTO 0) ;   -- sel1
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  sel2 : out bit_vector(1 DOWNTO 0) ;   -- sel2
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  sel3 : out bit_vector(1 DOWNTO 0) ;   -- sel3
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  vdd : in BIT; -- vdd
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  vss : in BIT  -- vss
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  );
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END cfb;
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-- Architecture Declaration
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37 
ARCHITECTURE VBE OF cfb IS
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  SIGNAL current_state : REG_VECTOR(3 DOWNTO 0) REGISTER;       -- current_state
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  SIGNAL current_state_s14 : BIT;               -- current_state_s14
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  SIGNAL next_state_s14 : BIT;          -- next_state_s14
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  SIGNAL current_state_s13 : BIT;               -- current_state_s13
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  SIGNAL next_state_s13 : BIT;          -- next_state_s13
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  SIGNAL current_state_s12 : BIT;               -- current_state_s12
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  SIGNAL next_state_s12 : BIT;          -- next_state_s12
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  SIGNAL current_state_s11 : BIT;               -- current_state_s11
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  SIGNAL next_state_s11 : BIT;          -- next_state_s11
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  SIGNAL current_state_s10 : BIT;               -- current_state_s10
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  SIGNAL next_state_s10 : BIT;          -- next_state_s10
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  SIGNAL current_state_s9 : BIT;                -- current_state_s9
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  SIGNAL next_state_s9 : BIT;           -- next_state_s9
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  SIGNAL current_state_s8 : BIT;                -- current_state_s8
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  SIGNAL next_state_s8 : BIT;           -- next_state_s8
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  SIGNAL current_state_s7 : BIT;                -- current_state_s7
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  SIGNAL next_state_s7 : BIT;           -- next_state_s7
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  SIGNAL current_state_s6 : BIT;                -- current_state_s6
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  SIGNAL next_state_s6 : BIT;           -- next_state_s6
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  SIGNAL current_state_s5 : BIT;                -- current_state_s5
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  SIGNAL next_state_s5 : BIT;           -- next_state_s5
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  SIGNAL current_state_s4 : BIT;                -- current_state_s4
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  SIGNAL next_state_s4 : BIT;           -- next_state_s4
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  SIGNAL current_state_s3 : BIT;                -- current_state_s3
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  SIGNAL next_state_s3 : BIT;           -- next_state_s3
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  SIGNAL current_state_s2 : BIT;                -- current_state_s2
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  SIGNAL next_state_s2 : BIT;           -- next_state_s2
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  SIGNAL current_state_s1 : BIT;                -- current_state_s1
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  SIGNAL next_state_s1 : BIT;           -- next_state_s1
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  SIGNAL current_state_s0 : BIT;                -- current_state_s0
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  SIGNAL next_state_s0 : BIT;           -- next_state_s0
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  SIGNAL next_state : BIT_VECTOR(3 DOWNTO 0);   -- next_state
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71 
BEGIN
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  next_state(0) <= (next_state_s0 OR next_state_s3 OR next_state_s4
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OR next_state_s6 OR next_state_s10 OR
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next_state_s11 OR next_state_s13);
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  next_state(1) <= (next_state_s0 OR next_state_s5 OR next_state_s6
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OR next_state_s7 OR next_state_s9 OR next_state_s11
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 OR next_state_s12);
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  next_state(2) <= (next_state_s0 OR next_state_s2 OR next_state_s4
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OR next_state_s9 OR next_state_s10 OR
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next_state_s12 OR next_state_s14);
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  next_state(3) <= (next_state_s2 OR next_state_s7 OR next_state_s8
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OR next_state_s9 OR next_state_s10 OR
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next_state_s11 OR next_state_s13);
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  next_state_s0 <= '0';
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  current_state_s0 <= (current_state(2) AND current_state(1) AND
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current_state(0));
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  next_state_s1 <= (current_state_s0 OR (current_state_s1 AND (NOT(
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dt_ready) OR NOT(key_ready))));
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  current_state_s1 <= (NOT(current_state(3)) AND NOT(current_state(2))
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AND NOT(current_state(1)) AND NOT(current_state(0)));
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  next_state_s2 <= (current_state_s1 AND first_dt AND dt_ready AND
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key_ready);
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  current_state_s2 <= (current_state(3) AND current_state(2) AND NOT(
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current_state(1)) AND NOT(current_state(0)));
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  next_state_s3 <= current_state_s2;
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  current_state_s3 <= (NOT(current_state(3)) AND NOT(current_state(2))
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AND NOT(current_state(1)) AND current_state(0));
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  next_state_s4 <= current_state_s3;
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  current_state_s4 <= (NOT(current_state(3)) AND current_state(2) AND
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NOT(current_state(1)) AND current_state(0));
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  next_state_s5 <= (current_state_s1 AND NOT(first_dt) AND dt_ready
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AND key_ready);
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  current_state_s5 <= (NOT(current_state(3)) AND NOT(current_state(2))
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AND current_state(1) AND NOT(current_state(0)));
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  next_state_s6 <= current_state_s5;
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  current_state_s6 <= (NOT(current_state(3)) AND NOT(current_state(2))
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AND current_state(1) AND current_state(0));
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  next_state_s7 <= (current_state_s4 OR current_state_s6);
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  current_state_s7 <= (current_state(3) AND NOT(current_state(2)) AND
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current_state(1) AND NOT(current_state(0)));
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  next_state_s8 <= (current_state_s7 OR (current_state_s8 AND (NOT(
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dt_ready) OR NOT(finish))));
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  current_state_s8 <= (current_state(3) AND NOT(current_state(2)) AND
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NOT(current_state(1)) AND NOT(current_state(0)));
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  next_state_s9 <= (current_state_s8 AND dt_ready AND finish);
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  current_state_s9 <= (current_state(3) AND current_state(2) AND
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current_state(1));
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  next_state_s10 <= (current_state_s9 AND e);
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  current_state_s10 <= (current_state(3) AND current_state(2) AND
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current_state(0));
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  next_state_s11 <= (current_state_s9 AND NOT(e));
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  current_state_s11 <= (current_state(3) AND current_state(1) AND
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current_state(0));
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  next_state_s12 <= (current_state_s10 OR current_state_s11);
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  current_state_s12 <= (NOT(current_state(3)) AND current_state(2) AND
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current_state(1) AND NOT(current_state(0)));
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  next_state_s13 <= current_state_s12;
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  current_state_s13 <= (current_state(3) AND NOT(current_state(2)) AND
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NOT(current_state(1)) AND current_state(0));
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  next_state_s14 <= (current_state_s13 OR current_state_s14);
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  current_state_s14 <= (NOT(current_state(3)) AND current_state(2) AND
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NOT(current_state(1)) AND NOT(current_state(0)));
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  label0 : BLOCK ((NOT((clk'STABLE)) AND NOT(clk)) = '1')
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  BEGIN
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    current_state(0) <= GUARDED (next_state(0) OR active);
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  END BLOCK label0;
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  label1 : BLOCK ((NOT((clk'STABLE)) AND NOT(clk)) = '1')
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  BEGIN
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    current_state(1) <= GUARDED (next_state(1) OR active);
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  END BLOCK label1;
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  label2 : BLOCK ((NOT((clk'STABLE)) AND NOT(clk)) = '1')
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  BEGIN
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    current_state(2) <= GUARDED (next_state(2) OR active);
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  END BLOCK label2;
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  label3 : BLOCK ((NOT((clk'STABLE)) AND NOT(clk)) = '1')
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  BEGIN
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    current_state(3) <= GUARDED (next_state(3) AND NOT(active));
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  END BLOCK label3;
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150 
sel3(0) <= ((current_state_s5 AND NOT(active)) OR (
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current_state_s7 AND NOT(active)) OR (current_state_s8 AND NOT(
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active)) OR (current_state_s9 AND NOT(active)));
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154 
sel3(1) <= (active OR (current_state_s0 AND NOT(active)) OR
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(current_state_s1 AND NOT(active)) OR (
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current_state_s2 AND NOT(active)) OR (current_state_s3 AND NOT(
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active)) OR (current_state_s4 AND NOT(active)) OR (
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current_state_s6 AND NOT(active)) OR (current_state_s10 AND NOT(
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active)) OR (current_state_s11 AND NOT(active)) OR (
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current_state_s12 AND NOT(active)) OR (current_state_s13 AND NOT(
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active)) OR (current_state_s14 AND NOT(active)));
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163 
sel2(0) <= ((current_state_s3 AND NOT(active)) OR (
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current_state_s5 AND NOT(active)));
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sel2(1) <= (active OR (current_state_s0 AND NOT(active)) OR
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(current_state_s1 AND NOT(active)) OR (
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current_state_s2 AND NOT(active)) OR (current_state_s4 AND NOT(
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active)) OR (current_state_s6 AND NOT(active)) OR (
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current_state_s7 AND NOT(active)) OR (current_state_s8 AND NOT(
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active)) OR (current_state_s9 AND NOT(active)) OR (
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current_state_s10 AND NOT(active)) OR (current_state_s11 AND NOT(
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active)) OR (current_state_s12 AND NOT(active)) OR (
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current_state_s13 AND NOT(active)) OR (current_state_s14 AND NOT(
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active)));
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177 
sel1(0) <= ((current_state_s1 AND first_dt AND dt_ready AND
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key_ready AND NOT(active)) OR (current_state_s2 AND NOT(
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active)) OR (current_state_s9 AND NOT(e) AND NOT(active
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)));
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182 
sel1(1) <= (active OR (current_state_s0 AND NOT(active)) OR
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(current_state_s1 AND (NOT(first_dt) OR NOT(
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dt_ready) OR NOT(key_ready)) AND NOT(active)) OR (
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current_state_s3 AND NOT(active)) OR (current_state_s4 AND NOT(
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active)) OR (current_state_s5 AND NOT(active)) OR (
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current_state_s6 AND NOT(active)) OR (current_state_s7 AND NOT(
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active)) OR (current_state_s8 AND NOT(active)) OR (
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current_state_s10 AND NOT(active)) OR (current_state_s11 AND NOT(
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active)) OR (current_state_s12 AND NOT(active)) OR (
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current_state_s13 AND NOT(active)) OR (current_state_s14 AND NOT(
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active)));
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194 
en_out <= ((current_state_s10 AND NOT(active)) OR (
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current_state_s11 AND NOT(active)));
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en_rcbc <= '0';
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199 
en_iv <= ((current_state_s1 AND NOT(first_dt) AND dt_ready
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 AND key_ready AND NOT(active)) OR (
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current_state_s2 AND NOT(active)));
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203 
en_in <= ((current_state_s1 AND first_dt AND dt_ready AND
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key_ready AND NOT(active)) OR (current_state_s8 AND
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dt_ready AND finish AND NOT(active)) OR (current_state_s9
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 AND NOT(active)));
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208 
cke_b_mode <= ((current_state_s0 AND NOT(active)) OR (
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current_state_s1 AND NOT(active)) OR (current_state_s2 AND NOT(
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active)) OR (current_state_s3 AND NOT(active)) OR (
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current_state_s4 AND NOT(active)) OR (current_state_s5 AND NOT(
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active)) OR (current_state_s6 AND NOT(active)) OR (
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current_state_s7 AND NOT(active)) OR (current_state_s8 AND NOT(
214 
active)) OR (current_state_s9 AND NOT(active)) OR (
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current_state_s10 AND NOT(active)) OR (current_state_s11 AND NOT(
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active)) OR (current_state_s12 AND NOT(active)) OR (
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current_state_s13 AND NOT(active)) OR (current_state_s14 AND NOT(
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active)));
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220 
cp_ready <= (current_state_s12 AND NOT(active));
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222 
emp_buf <= ((current_state_s1 AND first_dt AND dt_ready AND
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key_ready AND NOT(active)) OR (current_state_s8 AND
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dt_ready AND finish AND NOT(active)) OR (current_state_s9
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 AND NOT(active)));
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227 
s_gen_key <= ((current_state_s0 AND NOT(active)) OR (
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current_state_s1 AND NOT(active)) OR (current_state_s2 AND NOT(
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active)) OR (current_state_s3 AND NOT(active)) OR (
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current_state_s4 AND NOT(active)) OR (current_state_s5 AND NOT(
231 
active)) OR (current_state_s6 AND NOT(active)) OR (
232 
current_state_s7 AND NOT(active)) OR (current_state_s8 AND NOT(
233 
active)) OR (current_state_s9 AND NOT(active)) OR (
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current_state_s10 AND NOT(active)) OR (current_state_s11 AND NOT(
235 
active)) OR (current_state_s12 AND NOT(active)) OR (
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current_state_s13 AND NOT(active)) OR (current_state_s14 AND NOT(
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active)));
238 
 
239 
s_mesin <= ((current_state_s4 AND NOT(active)) OR (
240 
current_state_s6 AND NOT(active)) OR (current_state_s7 AND NOT(
241 
active)) OR (current_state_s8 AND (NOT(dt_ready) OR NOT
242 
(finish)) AND NOT(active)));
243 
 
244 
e_mesin <= (active OR (current_state_s0 AND NOT(active)) OR
245 
(current_state_s1 AND NOT(active)) OR (
246 
current_state_s2 AND NOT(active)) OR (current_state_s3 AND NOT(
247 
active)) OR (current_state_s4 AND NOT(active)) OR (
248 
current_state_s5 AND NOT(active)) OR (current_state_s6 AND NOT(
249 
active)) OR (current_state_s7 AND NOT(active)) OR (
250 
current_state_s8 AND NOT(active)) OR (current_state_s9 AND NOT(
251 
active)) OR (current_state_s10 AND NOT(active)) OR (
252 
current_state_s11 AND NOT(active)) OR (current_state_s12 AND NOT(
253 
active)) OR (current_state_s13 AND NOT(active)) OR (
254 
current_state_s14 AND NOT(active)));
255 
 
256 
first_dt <= (active OR (current_state_s0 AND NOT(active)) OR
257 
(current_state_s1 AND NOT(active)) OR (
258 
current_state_s5 AND NOT(active)));
259 
END;

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