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-- VHDL data flow description generated from `counter`

--              date : Wed Mar 21 13:35:50 2001

-- Entity Declaration

ENTITY counter IS

  PORT (

  ck : in BIT;  -- ck

  i : in BIT;   -- i

  reset : in BIT;       -- reset

  o : out BIT;  -- o

  vdd : in BIT; -- vdd

  vss : in BIT  -- vss

  );

END counter;

-- Architecture Declaration

ARCHITECTURE VBE OF counter IS

  SIGNAL current_state : REG_VECTOR(2 DOWNTO 0) REGISTER;       -- current_state

  SIGNAL current_state_s4 : BIT;                -- current_state_s4

  SIGNAL next_state_s4 : BIT;           -- next_state_s4

  SIGNAL current_state_s3 : BIT;                -- current_state_s3

  SIGNAL next_state_s3 : BIT;           -- next_state_s3

  SIGNAL current_state_s2 : BIT;                -- current_state_s2

  SIGNAL next_state_s2 : BIT;           -- next_state_s2

  SIGNAL current_state_s1 : BIT;                -- current_state_s1

  SIGNAL next_state_s1 : BIT;           -- next_state_s1

  SIGNAL current_state_s0 : BIT;                -- current_state_s0

  SIGNAL next_state_s0 : BIT;           -- next_state_s0

  SIGNAL next_state : BIT_VECTOR(2 DOWNTO 0);   -- next_state

BEGIN

  next_state(0) <= (next_state_s0 OR next_state_s3 OR next_state_s4);

  next_state(1) <= (next_state_s0 OR next_state_s4);

  next_state(2) <= (next_state_s2 OR next_state_s3 OR next_state_s4);

  next_state_s0 <= ((current_state_s0 AND NOT(i)) OR (

current_state_s1 AND NOT(i)) OR (current_state_s2 AND NOT(i)) OR

(current_state_s3 AND NOT(i)) OR (current_state_s4

 AND NOT(i)));

  current_state_s0 <= (NOT(current_state(2)) AND current_state(1));

  next_state_s1 <= (current_state_s0 AND i);

  current_state_s1 <= (NOT(current_state(2)) AND NOT(current_state(1)));

  next_state_s2 <= (current_state_s1 AND i);

  current_state_s2 <= (current_state(2) AND NOT(current_state(0)));

  next_state_s3 <= (current_state_s2 AND i);

  current_state_s3 <= (NOT(current_state(1)) AND current_state(0));

  next_state_s4 <= ((current_state_s3 AND i) OR (current_state_s4

AND i));

  current_state_s4 <= (current_state(2) AND current_state(1));

  label0 : BLOCK ((NOT((ck'STABLE)) AND NOT(ck)) = '1')

  BEGIN

    current_state(0) <= GUARDED (next_state(0) OR reset);

  END BLOCK label0;

  label1 : BLOCK ((NOT((ck'STABLE)) AND NOT(ck)) = '1')

  BEGIN

    current_state(1) <= GUARDED (next_state(1) OR reset);

  END BLOCK label1;

  label2 : BLOCK ((NOT((ck'STABLE)) AND NOT(ck)) = '1')

  BEGIN

    current_state(2) <= GUARDED (next_state(2) AND NOT(reset));

  END BLOCK label2;

o <= (current_state_s4 AND NOT(reset));

END;