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[/] [idea/] [trunk/] [behavioral/] [main control/] [ecb.vbe] - Blame information for rev 10

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1 6 marta 
-- VHDL data flow description generated from `ecb`
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--              date : Sat Sep  1 20:14:57 2001
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-- Entity Declaration
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ENTITY ecb IS
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  PORT (
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  active : in BIT;      -- active
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  clk : in BIT; -- clk
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  cke : in BIT; -- cke
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  key_ready : in BIT;   -- key_ready
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  finish : in BIT;      -- finish
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  req_cp : in BIT;      -- req_cp
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  e : in BIT;   -- e
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  e_mesin : out BIT;    -- e_mesin
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  s_mesin : out BIT;    -- s_mesin
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  s_gen_key : out BIT;  -- s_gen_key
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  emp_buf : out BIT;    -- emp_buf
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  cp_ready : out BIT;   -- cp_ready
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  cke_b_mode : out BIT; -- cke_b_mode
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  en_in : out BIT;      -- en_in
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  en_iv : out BIT;      -- en_iv
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  en_rcbc : out BIT;    -- en_rcbc
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  en_out : out BIT;     -- en_out
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  sel1 : out bit_vector(1 DOWNTO 0) ;   -- sel1
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  sel2 : out bit_vector(1 DOWNTO 0) ;   -- sel2
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  sel3 : out bit_vector(1 DOWNTO 0) ;   -- sel3
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  vdd : in BIT; -- vdd
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  vss : in BIT  -- vss
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  );
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END ecb;
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-- Architecture Declaration
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ARCHITECTURE VBE OF ecb IS
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  SIGNAL current_state : REG_VECTOR(2 DOWNTO 0) REGISTER;       -- current_state
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  SIGNAL current_state_s6 : BIT;                -- current_state_s6
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  SIGNAL next_state_s6 : BIT;           -- next_state_s6
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  SIGNAL current_state_s5 : BIT;                -- current_state_s5
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  SIGNAL next_state_s5 : BIT;           -- next_state_s5
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  SIGNAL current_state_s4 : BIT;                -- current_state_s4
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  SIGNAL next_state_s4 : BIT;           -- next_state_s4
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  SIGNAL current_state_s3 : BIT;                -- current_state_s3
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  SIGNAL next_state_s3 : BIT;           -- next_state_s3
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  SIGNAL current_state_s2 : BIT;                -- current_state_s2
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  SIGNAL next_state_s2 : BIT;           -- next_state_s2
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  SIGNAL current_state_s1 : BIT;                -- current_state_s1
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  SIGNAL next_state_s1 : BIT;           -- next_state_s1
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  SIGNAL current_state_s0 : BIT;                -- current_state_s0
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  SIGNAL next_state_s0 : BIT;           -- next_state_s0
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  SIGNAL next_state : BIT_VECTOR(2 DOWNTO 0);   -- next_state
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BEGIN
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  next_state(0) <= (next_state_s2 OR next_state_s5 OR next_state_s6);
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  next_state(1) <= (next_state_s1 OR next_state_s4 OR next_state_s5);
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  next_state(2) <= (next_state_s0 OR next_state_s1 OR next_state_s5
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OR next_state_s6);
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  next_state_s0 <= (current_state_s0 AND NOT(cke));
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  current_state_s0 <= (current_state(2) AND NOT(current_state(1)) AND
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NOT(current_state(0)));
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  next_state_s1 <= ((current_state_s0 AND cke) OR (current_state_s1
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AND NOT(key_ready)));
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  current_state_s1 <= (current_state(2) AND current_state(1) AND NOT(
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current_state(0)));
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  next_state_s2 <= (current_state_s1 AND key_ready);
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  current_state_s2 <= (NOT(current_state(2)) AND current_state(0));
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  next_state_s3 <= (current_state_s2 OR (current_state_s3 AND NOT(
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finish)));
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  current_state_s3 <= (NOT(current_state(2)) AND NOT(current_state(1))
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AND NOT(current_state(0)));
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  next_state_s4 <= (current_state_s3 AND finish);
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  current_state_s4 <= (NOT(current_state(2)) AND current_state(1));
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  next_state_s5 <= (current_state_s4 OR (current_state_s5 AND NOT(
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req_cp)));
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  current_state_s5 <= (current_state(1) AND current_state(0));
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  next_state_s6 <= ((current_state_s5 AND req_cp) OR
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current_state_s6);
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  current_state_s6 <= (current_state(2) AND NOT(current_state(1)) AND
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current_state(0));
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  label0 : BLOCK ((NOT((clk'STABLE)) AND NOT(clk)) = '1')
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  BEGIN
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    current_state(0) <= GUARDED (next_state(0) AND NOT(active));
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  END BLOCK label0;
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  label1 : BLOCK ((NOT((clk'STABLE)) AND NOT(clk)) = '1')
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  BEGIN
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    current_state(1) <= GUARDED (next_state(1) AND NOT(active));
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  END BLOCK label1;
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  label2 : BLOCK ((NOT((clk'STABLE)) AND NOT(clk)) = '1')
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  BEGIN
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    current_state(2) <= GUARDED (next_state(2) OR active);
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  END BLOCK label2;
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sel3(0) <= '0';
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sel3(1) <= (active OR (current_state_s0 AND NOT(active)) OR
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(current_state_s1 AND NOT(active)) OR (
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current_state_s2 AND NOT(active)) OR (current_state_s3 AND NOT(
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active)) OR (current_state_s4 AND NOT(active)) OR (
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current_state_s5 AND NOT(active)) OR (current_state_s6 AND NOT(
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active)));
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sel2(0) <= '0';
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sel2(1) <= (active OR (current_state_s0 AND NOT(active)) OR
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(current_state_s1 AND NOT(active)) OR (
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current_state_s2 AND NOT(active)) OR (current_state_s3 AND NOT(
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active)) OR (current_state_s4 AND NOT(active)) OR (
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current_state_s5 AND NOT(active)) OR (current_state_s6 AND NOT(
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active)));
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sel1(0) <= ((current_state_s2 AND NOT(active)) OR (
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current_state_s3 AND NOT(active)) OR (current_state_s4 AND NOT(
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active)) OR (current_state_s5 AND NOT(active)) OR (
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current_state_s6 AND NOT(active)));
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sel1(1) <= (active OR (current_state_s0 AND NOT(active)) OR
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(current_state_s1 AND NOT(active)));
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en_out <= (current_state_s3 AND NOT(active) AND finish);
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en_rcbc <= '0';
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en_iv <= '0';
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en_in <= (current_state_s1 AND NOT(active) AND key_ready);
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cke_b_mode <= ((current_state_s0 AND NOT(active) AND cke) OR (
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current_state_s1 AND NOT(active)) OR (current_state_s2 AND NOT(
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active)) OR (current_state_s3 AND NOT(active)) OR (
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current_state_s4 AND NOT(active)) OR (current_state_s5 AND NOT(
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active)) OR (current_state_s6 AND NOT(active)));
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cp_ready <= ((current_state_s4 AND NOT(active)) OR (
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current_state_s5 AND NOT(active) AND NOT(req_cp)));
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emp_buf <= ((current_state_s2 AND NOT(active)) OR (
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current_state_s3 AND NOT(active) AND NOT(finish)));
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s_gen_key <= ((current_state_s0 AND NOT(active) AND cke) OR (
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current_state_s1 AND NOT(active)) OR (current_state_s2 AND NOT(
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active)) OR (current_state_s3 AND NOT(active)) OR (
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current_state_s4 AND NOT(active)) OR (current_state_s5 AND NOT(
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active)) OR (current_state_s6 AND NOT(active)));
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s_mesin <= ((current_state_s2 AND NOT(active)) OR (
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current_state_s3 AND NOT(active) AND NOT(finish)));
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e_mesin <= ((e AND active) OR (current_state_s0 AND e AND
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NOT(active)) OR (current_state_s1 AND e AND NOT(
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active)) OR (current_state_s2 AND e AND NOT(active)) OR
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 (current_state_s3 AND e AND NOT(active)) OR (
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current_state_s4 AND e AND NOT(active)) OR (current_state_s5 AND
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e AND NOT(active)) OR (current_state_s6 AND e AND
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NOT(active)));
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END;

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